Rohan Juneja Email & Phone Number

United States

Singapore

• Ph.D. student co-supervised by Prof Peh Li Shiuan and Prof Tulika Mitra.► Contributed to designing REACT, an accelerator for transfer learning for wearables, guided by Prof Li-Shiuan Peh and Prof Weng-Fai Wong. (Paper.
• It proposes heterogeneous cores that can support both training and inference.
• The architecture is NoC-centric, with weights, features and gradients distributed across cores, accessed, and computed efficiently through software-configurable NoCs.
• REACT’s online learning realizes up to 75% accuracy improvement and is up to 25× faster and 520× more energy-efficient than state-of-the-art accelerators with similar memory and computation footprint.► Contributed to.

Singapore

Worked at AMD CTO Lab.

Singapore

Worked on Dynamic Reconfigurable Processor (DRP).

Bengaluru, Karnataka, India

• Worked as a CPU design engineer for Qualcomm Snapdragon Processors.
• Responsible for multi-clock domain and Low Power(UPF) RTL delivery of ARM Kryo cores in Snapdragon 765G and other medium, high tier and compute chips.
• Responsible for restructuring memory model RTL to support partial power gating.
• Exposure to Power ManagerIP, DCVS, and Low Power Modes using ARM’s P-channel, and boot RTL in Snapdragon CPUs.
• Experienced in writing SystemVerilog assertions, code coverage, and functional coverage closure.
• Experienced in Synthesis flows, reviewing Design Constraints, timing arcs, and optimized registers==Technologies==Language: Verilog, Python/ Shell scriptingTools: Verdi, VCS, DC, SpyglassTechnologies: CDC, PLDRC and.

Singapore

► Worked at Hardware and Embedded Systems Lab (HESL) with Prof. Lam Siew Kei► Paper on dynamic integrity model is published in IEEE Transactions on VLSI, DATE 2020, and ASP-DAC 2021. (Please check the publications section below)Memory authentication is important for embedded systems and to counter this, various hardware memory integrity checking schemes.

New Delhi Area, India

► Worked at Advanced Multicore Systems Lab with Prof. Sujay Deb► Paper submitted in IEEE Transactions on ComputersCache coherence protocols are provided to ensure that multiple cached copies of a single memory block are kept up-to-date. But with rapid increase in the number of cores, scalability of cache coherence protocols is very difficult to achieve..

New Delhi Area, India

► Worked at Advanced Multicore Systems Lab with Prof. Sujay Deb► Paper published in ISQED 2018. (Please check publications section)► Received travel grant of around 2000USDs to present the paper at Santa Clara, California.With many core processors gaining significance for high-performance computing applications, there is a great need for designing.

Doctor Of Philosophy - Phd, Computer Science

Ph.D. student at the School of Computing. Check the Experience section for further details on Projects.

Computer Science And Engineering

Exchange student Fall 2017. Worked as a Research Assistant under Dr. Lam Siew Kei. Check the Experience section for further details.

Bachelor Of Technology (B.Tech.), Electronics And Communication Engineering

Completed my bachelor's degree from IIIT Delhi with a major in Electronics and Communication Engineering. During my bachelor's I have been.

Education record

Activities and Societies: Media Panel, House Captain