Justin Leung Email and Phone Number
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Qualification highlights:• Chip Design Expert and Key Contributor on numerous Intel Microprocessor Designs on leading-edge process technologies (0.25m to 22nm process nodes)• Manager and Technical Lead for Clock Generation, Distribution, and Methodology• Experienced Technologist – Power Delivery, Packaging, Low Power, and Thermal Design• Manager of Electrical and Mechanical Test Hardware Modeling Group.• 20-years of Semiconductor Experience spanning Design, Manufacturing, and Process Development• Strong Experience with highly complex, multi-GHz microprocessor design efforts providing both Technical and Managerial Leadership.
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KeyprRancho Palos Verdes, Ca, Us -
Vp Hardware EngineeringKeypr Nov 2016 - Aug 2019Los Angeles, Ca, Us
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Director Of Hardware EngineeringKeypr Mar 2015 - Dec 2018Los Angeles, Ca, Us
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Vp Hardware And Data EngineeringIntelity Mar 2015 - Aug 2019Los Angeles, California, Us -
Design ManagerIntel Corporation Nov 2010 - Sep 2012Santa Clara, California, UsSanta Clara Processor Division* Clock Design Manager – managed and led extended team of 10-12 team members. Led team in all aspects of clocking including clock architecture, floorplanning, clock tools and methodology development, timing, design convergence, clocking audits, and tapeout signoff.• Clock Technical Leader - Technical owner of all Clock design aspects of leading edge 22nm Intel server CPU. Developed global skew and jitter methodologies and budgets encompassing within domain and cross-frequency skew budgets. • Collaborated with corporate clock design experts on assessing and evaluating clock design trends in areas of Clock Tools and Clock Methodology. -
Technical LeadIntel Corporation Jan 2009 - Oct 2010Santa Clara, California, UsMicroprocessor Division* Clock distribution architect for deep-submicron SOC graphics-subsystem. * Developed a modular, low-power, multi-frequency, multi-power plane clock distribution implemented with a new clock spine design tool. * Clock methodology owner responsible for clock crossings, clocking design rules, clocking interfaces, clocking coordination acrosst a multi-site design team.
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Senior Staff Design EngineerIntel Corporation Jan 2006 - Dec 2008Santa Clara, California, UsEnterprise Microprocessor Division - 45nm CPU design* Clock distribution owner for first x86-based 8-core Xeon server CPU family (Xeon 7500 series)* Developed a novel, low-power, clock spine design to drive an ultra-low skew clock across a 24MB modular cache. * Custom designed and verified a global deskew spine alignment mechanism to enable post-Si skew adjustment.* Provided technical mentorship and design feedback to India-based CPU design team.
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Senior Staff Design EngineerIntel Corporation Jan 2004 - Dec 2005Santa Clara, California, UsEnterprise Microprocessor Division - 65nm design* Clock distribution design for first x86-based monolithic dual-core server CPU family (Xeon 7100 series).* Led floorplan and layout implementation of global clock network featuring dual frequency global clock scheme to optimize core and cache power consumption. * Debugged and characterized clocking issues and performance through tapeout and multiple steppings.
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Staff Design EngineerIntel Corporation Jun 2000 - Dec 2003Santa Clara, California, UsEnterprise Microprocesso Division - 130nm designs* Technology and special circuits design on two 130nm enterprise server CPU chip designs.* Packaging: silicon-package design interface, C4 bump pattern designer* Circuits: Owned power-up sensor, thermal sensors, and thermal diode designs* Thermals: Owned pre-Si power/thermal model development and post-Si thermals characterization* Power Delivery: Power grid modelling, decap methodology, power delivery audits.
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Modeling Group ManagerIntel Corporation Feb 1999 - Aug 1999Santa Clara, California, UsManaged team of senior engineers providing advanced electrical and mechanical modeling for test hardware development. Led pathfinding team which constructed a 5-generation Sort/Probing pathfinding roadmap.
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Program LeaderIntel Corporation Jun 1998 - Feb 1999Santa Clara, California, UsIntel Test Tooling Operation* Led 0.18um buckling beam sort probing development team addressing HVM lifetime improvements and second source strategy.
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Senior Development EngineerIntel Corporation Jan 1997 - May 1998Santa Clara, California, UsIntel Test Tooling Operation* Lead development engineer on discovery and development of Cobra C4 probe wafer sort hardware technology. * Cobra technology developed and deployed into 0.25um HVM production one quarter ahead of original schedule. * Managed successful first article deliveries from emgerging C4 probecard supplies and performed electrical and mechanical characterization studies.
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Graduate Research Assistant - Center For Integrated SystemsStanford University Sep 1992 - Dec 1996Stanford, Ca, Us* Developed an active substrate membrane probe card technology* First demonstration of the monolithic integration of BiCMOS test circuitry with a silicon-based probecard. -
Src Graduate Intern - Known Good Die GroupMotorola Mobility (A Lenovo Company) Jun 1993 - Sep 1993Chicago, Illinois, Us* Performed experimental evaluation of known good die burn-in technology -
Graduate Intern - Multi-Level Interconnect GroupTexas Instruments Jun 1992 - Sep 1992Dallas, Tx, Us* Evaluated pattern resist etch-back as a wafer processing global planarization technique.
Justin Leung Skills
Justin Leung Education Details
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Stanford UniversityElectrical Engineering -
Stanford UniversityElectrical Engineering
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University Of California, BerkeleyElectrical Engineering
Frequently Asked Questions about Justin Leung
What company does Justin Leung work for?
Justin Leung works for Keypr
What is Justin Leung's role at the current company?
Justin Leung's current role is Technical Leader, Engineering Management.
What is Justin Leung's email address?
Justin Leung's email address is ju****@****tel.com
What is Justin Leung's direct phone number?
Justin Leung's direct phone number is +131059*****
What schools did Justin Leung attend?
Justin Leung attended Stanford University, Stanford University, University Of California, Berkeley.
What skills is Justin Leung known for?
Justin Leung has skills like Hardware Architecture, Signal Integrity, Floorplanning, Analog Circuit Design, Debugging, System Verilog, Reliability, Electronics Packaging, Rtl Design, Ic, Microprocessors, Processors.
Who are Justin Leung's colleagues?
Justin Leung's colleagues are Caroline Pepper.
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