Founded E-motions Engineering LLC with a vision to blend modern science and traditional techniques to enhance human well-being and productivity.-Consulted with and coached leaders and investors of conscious companies to evaluate, elevate, and execute world changing visions and strategy.-Pioneered the development and implementation of innovative approaches to optimize human performance, utilizing expertise in electrical engineering, coaching, yoga, meditation, nutrition, fitness, and personal development.-Authored the Amazon best-selling book "Engineered to Love: Going Beyond Success to Fulfillment using Practical Tools to Relax, Recharge, and Reconnect," providing practical insights into achieving personal and professional fulfillment.-Created and hosts "Engineering Emotions and Energy with Justin Wenck, Ph.D," a platform to guide listeners in personal and organizational transformation, stress management, life optimization, and the impacts of technology on the human experience.-Led the design and execution of diverse projects integrating technology and human-centric principles to foster holistic development and stress reduction.-Championed a culture of continuous learning and growth, both internally and for clients.Developed and maintained partnerships and collaborations to expand the reach and impact of the company's initiatives and programs.

Strategic Planning and Decision Making: Provide guidance and support on shaping theoverall business strategic vision and decision making, collaborating with Cofounders andleadership to identify risks and opportunities in context of the business’s needs and goals.Operational Design: Advise on improving organizational design and operationaleffectiveness, including but not limited to shaping team roles & responsibilities, structure,workflows, and accountability systems for employees and external contributors (consultants,advisors, vendors).Product: Provide strategic insights and guidance on product efforts, including featureprioritization, roadmapping, user experience enhancements, and execution feasibility;collaborate with product teams to align the product roadmap with Mattermore's overallstrategic objectives, ensuring a focus on innovation and customer needs.Technology and R&D: Advise on the development, implementation, and purchase of coretechnologies and research & development initiatives; participate in tech brainstorming thatenhance Mattermore's product offerings and operational efficiency.Market Analysis and Expansion Strategies: Contribute to identifying current and emergingmarket trends around customer expansion and customer value-add opportunities. Inform newmarkets or segments strategies, including competitive analysis, partnership opportunities, andmarket entry tactics

I specialize in leveraging Positive Intelligence (PQ) to enhance mental fitness and emotional intelligence in the tech industry. My approach combines deep technical expertise with advanced coaching techniques, focusing on improving resilience, creativity, and leadership among engineers, developers, and executives. Through personalized coaching and practical tools, I empower clients to overcome self-sabotaging behaviors, fostering environments that prioritize innovation, well-being, and sustainable growth. My work extends to authoring "Engineered to Love" and hosting the Engineering Emotions and Energy Podcast, where I share insights on achieving fulfillment beyond conventional success.

Spearheaded a range of post-merger technical projects and organizational initiatives, leveraging deep expertise in memory circuit design, product validation, and technical marketing engineering to drive innovation and mentorship across the Datacenter Division.-Led and integrated multifaceted start-up initiatives, coordinating cross-functional, -geo, -company teams and 3rd parties, excelling in dual system roles and overseeing critical forums (SysDebug/ValCoord) to ensure meticulous attention to manufacturing, compliance, firmware, hardware, etc. demonstrating flexibility and innovative problem-solving.-Modernized ASIC & SSD strategic planning manual Excel method to automated & traceable Requirements for JIRA (R4J) that aligned with SSD Development/Engineering flow. Utilized analytical skills to forecast requirement issues and their potential impact, leading to proactive adjustments and continued program success.-Reduced cost and employee dissatisfaction by orchestrating 'Effective Meetings' initiative the SIE org as measure by surveys. Developed and delivered training modules, drove senior leadership to prioritize and take actions on results. -Integrated the Quality and Reliability Criteria (QRC) of Intel/SKH post-merger, representing System Integration in QRC Workgroup to create Solidigm’s own best-in-class revision to streamline processes and bolstered efficiency.-Optimized recruiting, resume review, and interview tactics, which increased hiring flexibility and early candidate engagement using 10+ years of technical and company cultural experience. -Developed grade level expectations and R&R’s for key department roles (PEL/SI/Debug Dev) to improve career clarity and engagement. Provided senior mentorship and coaching.-Increased product execution predictability by working with key executives & stakeholders to include Product Health Indicator (PHI) in executive updates.

Delivers end-to-end full product master test plan across multiple cross-functional validation teams. Reports product quality and testing status to executive management and customer teams. Drives evolution of quality related processes to scale across multiple product lines and customers.-Received Department Recognition Award for outstanding execution to pull in product schedule by 6 weeks. Reduced qualification cycle time by developing full stack emerging storage workload validation strategy.-Saved millions of dollars in manufacturing costs through data-based decision-making methodology for SSD PCB architectural SKU Strategy that incorporated host and ONFI performance, financial, and engineering tradeoffs.-Improved customer relations by correcting requirements gap through creation of unified internal-customer, and industry (Emerging NVMe, PCIe, OCP, etc.) specifications. Wrote and published clear one-stop requirements through JIRA. -Initiated and organized cross-team reviews of product features, validation strategies and capabilities. This ensured sufficient budget for late change requests and enabled the Agile development process to have clear story point targets.-Developed Python checker to ensure product requirements were mapped to valid validation categories for test traceability and to enable parallel checking and reviewing across teams.

Promoted to Technical Marketing Engineering Manager responsible for technical definition of large scale datacenter PCIe SSD, the department’s technical collateral lead and new talent manager.Translate high-level storage product features into product technical requirements managing internal and external stakeholders (Application Engineers, Product Marketing Engineers, Customer Field Sales, and Customers), and supervise internal activities to meet customer commitments to design, test, and deliver products. Manage, recruit, interview, hire, train, and track progress of new department talent. Lead department’s technical collateral standards and automation. -Pulled-in customer specification gap analysis of next-gen flagship PCIe NAND product, to enable faster OEM ramp to next-gen 3D NAND to drive 1/3 of business unit revenue in the next few years.-Enabled next-gen PCIe ecosystem to expand available market as part of PCI-SIG Marketing Working Group.-Drove accountability and efficiency by documenting product requirements in both current and upcoming requirements database, Doors Next Generation, while driving proper test and validation planning. -Improved department’s collateral quality and creation efficiency through workgroup standards, publication of datasheets with new DITA XML content management system, creation of sighting report process and automation tool, and completion of FIO performance visualization tool. -Recruited the department’s most talented interns yet from top universities and mentored them to develop ground breaking efficiency tools.-Maximized business results by developing engineering resource efficient solutions to meet customer requirements in areas from variable sector sizes to form factors to supply chain.-Created product and technology collaterals for customer presentation given by self and field sales team.-Developed research projects with local university to improve technology and talent pipeline.

Communicate feature development and sighting resolution priorities to cross-functional engineering teams based on business and customer needs for NVMe PCIe SSDs, and supervise activities to meet design, test, and delivery commits. Deliver datasheets, sightings reports, customer letter content, spec gap analysis, and design reviews. Lead technical product definition of next gen 3D NAND PCIe SSD product family, translating high-level product features into technical requirements with customer, marketing, field, design and product engineering inputs. Recruit, onboard, train, and develop top undergraduate and graduate interns to deliver results for team, marketing department, and entire business group. Ensure an inclusive work environment, manage performance, plan and schedule tasks, and use judgment on a variety of problems requiring deviation from standard practices.

Datacenter platform integration, enterprise SSD debug, and Compatibility Validation Technical Lead for PCIe NAND SSDs.Lead cross-functional, cross-geo team from 1st check outs to Customer Samples for one the most complex and ambitious Enterprise SSD families in department history. Create test plans based on requirements and customer requests. Strategically planned test content and resources based on product roadmap, requirements, customer requests, and datacenter trends; reporting validation execution status to stakeholderds. Work with Marketing, Engineering, QA, etc. to debug issue to completion or adequate customer communication. Resolve customer issues through daily task forces. Manage from the middle by consistently and clearly communicating validation progress in relation to product milestones.-Enabled enterprise ecosystem by testing products at Platform Readiness Workshops.-Drove product to customer readiness quality, and PCI-SIG and NVMe Compliance Certifications. -Influenced Product Team to execute project as 3 separate products based on Customer/SKU alignment for optimal execution.-Optimized test server utilization by abstracting away irrelevant details.-Improved overall product portfolio TTM by driving debug of upstream products that would impact derivatives.-Reduced new firmware (FW) prep time from 1 day to 1 hour by having FW engineers in lab with “Win-Win” proposal.-Led diverse team to work nights and weekends to meet milestones for over 5 months with zero attrition.-Integrated latest server platforms into complex Compatibility Validation test environment-Sped Product Validation department validation transparency by quickly adopting real-time group visible indicators.-Influenced reuse of Test content and OS requirements across multiple product families.-Adapted to 5 business day pre-sighting SLA (Service Level Agreement) with 97% success once instituted.

Progressed from Analog Engineer working on several circuit blocks to critical circuit block owner in LPDDRX Memory Interface IP.Lead diverse, high-performing team—comprising Mask Designers, Circuit Design Engineers, Logic Designer, Logic Validator, Post-Si Validators-- through specification, design, implementation, and pre- and post-Si verification of a new Delay-Locked Loop (DLL), including analog circuit blocks and supporting RTL, for DDR/LPDDR memory interfaces on Intel’s most advanced technology. Consistently articulate a clear vision; create detailed project requirements and schedules; and demonstrate swift, well-informed decision making, enabling cross-geo teams to quickly iterate changes in circuits, layout, and logic to meet strict project deadlines. Keep design documentation up to date for future patent applications, industry presentations, and design iterations.-Designed and delivered silicon proven high-speed DLL for next-gen LPDDR for mobile SoC. -Ramped cross-org Post-Si Power-On team to enable functional BIOS within days of 1st Si. -Talks and IP Filings on DLL with uncalibrated Time-to-Digital Converter (TDC).-Improved PHY clocking architecture to meet high-speed timing while reducing power. -Optimized Analog/Digital partitioning to ease timing closure across clocking boundaries.-Awarded for influencing multiple project requirements, execution methodologies, and schedules.-Coordinated design execution among SD, PV, and DE teams to meet project milestones on schedule. -Leveraged network to speed inclusion of power sipping DLL Idle mode in uServer SOC.-Seamlessly handed off DLL design to cross-geo team.-Thru-Silicon-Via (TSV) WIO memory interface transceiver design. -Improved and promoted design methodologies across department: DLL Jitter and Phase Error budgeting; variation methodologies for full DLL, Phase Detectors, TDC’s, and Delay Cells; PrimeTime on custom blocks; and SharePoint for document sharing.

Excelled in Intel's Rotation Engineer Program (REP), a full-time, 18-month technical development program for top college graduates with technical degrees and strong leadership skills. Specified, implemented, and validated RTL for memory architecture research. Designed DDR I/O circuits and supported post-Si validation and debugging. -Quickly adapted to German culture and developed FPGA synthesizable and reconfigurable memory-sided cache in SystemVerilog to enable future non-volatile memory (NVM) architecture research.-Automated RTL validation by creating self-checking System Verilog tests and a Python environment to vary cache size, associativity, and replacement policy.

-Designed new voltage level-shifter architecture that reduced Vccmin and active power by 10% and S3 leakage by 50% compared to previous design.-Reduced time for level-shifter supply noise sensitivity analysis from several hours to less than one hour. Developed new Tx power supply analysis methodology that more accurately models the post-Si environment by working with circuit and cross-site power delivery owners. -Enabled completion of 80% of post-Si power-on exit criteria for DDR I/O IP within one week of SoC power-on. Trained new EV team members for validation execution-Provided hardware expertise to validation software tool developers. Defined validation procedures based on expert knowledge of DDR3 architecture, circuits, and test hooks.-Owned definition and enhancement of Python Automation Environment for DDR I/O circuit validation. Drove improvements in data quality and significant reductions in validation and project planning time. Improved team efficiency by implementing shared OneNote notebook and Visual SourceSafe to share data.

Researched, documented, published, and presented in the area of microscale energy harvester powered circuits and systems. · Met MOSIS deadline to finish proof-of-concept AC supply powered custom IC. · Designed, populated, soldered a PCB to test and characterize a custom IC. · Consulted with vendors to select test equipment and parts. · Troubleshot custom IC and FPGA programming and testing failures. · Reduced custom IC test time by automating test procedures. · Created new SRAM and DRAM cell designs for AC powered digital systems. · Modeled and evaluated design space for volume constrained systems. · Presented research findings at international conferences. · Reduced time to learn and use CAD tools for research group members by documenting tool flows on research group Wiki. · Managed 3 junior graduate students to complete 90nm digital CMOS standard cell library. · Trained and mentored both undergraduate and graduate students in related, but independent, research projects. · Improved 90nm digital CMOS design flow by editing the Calibre LVS rule deck.

Taught, monitored and evaluated up to 30 undergraduates in digital electronics labs. Graded lab work and exams. · Improved student lab performance by creating and giving lectures before lab.

Supported Test Development Engineers in creating test procedures for automated test equipment. Troubleshot and repaired high-speed digital boards at the component level. Worked on a multidisciplinary team to help resolve automated test equipment failures. Commented on usability of software, documents, and processes created by other engineers. Measured active and passive trace lengths on boards for calibration. Key Achievements: Created Perl and Excel scripts to automate common tasks in both Windows and UNIX environments.  Built and modified a custom digital pressure regulator for use on production floor