Jian Wang Email & Phone Number

I am an experienced FPGA and ASIC design and verification lead specializing in real time DSP and embedded processor design. I am passionate about building automation scripts and tools that improve productivity.I architect and implement FPGA for silicon validations. I am recognized for leading ASIC design teams to tape out and production. The DSPs I have worked on have been deployed in over 100 million xDSL ports worldwide. I contribute to each stage of designs, from specification, architecture, 3rd party IP qualification and integration, implementation, verification, emulation, synthesis, DFT constraints, static timing analysis, timing closure, post silicon validation, ATE vector generation, and production support.In collaboration with teams including system software, algorithm team, firmware, PCB hardware. I solve urgent issues quickly in the field. I develop and manage Python scripts for IC design database management, design automation, regression automation, C/C++ header file generation, ATE vector generation.Technical skills:- RTL design and verification in verilog/SystemVerilog/VHDL- Altera/Xilinx FPGA design, including planning, architecture, design verification, timing closure- Real-time DSP and embedded processor design- Synthesis and Primetime timing closureemail: jwang69@gmail.com

Listed skills include Soc, Embedded Systems, Asic, Semiconductors, and 22 others.

• 

  University Of Washington

  Dsp