Design and develop PDK Runsets for lower technology nodes,ensuring they align with process technology requirements and design constraints. This involves scripting, coding, and configuring parameters to facilitate smooth and accurate design flows. Develop physical layout verification design rule checker (DRC), Layout vs Schematic(LVS), Antenna runsets using industry standard EDA tools (Synopsys ICV,Siemens/Mentor Calibre, and Cadence Pegasus)I also own releasing Runsets to PDKs portal from where various customers could download kits for IP designs. Develop RTG for the runsets and rigorously test and validate runsets to ensure their adherence to design specifications and compatibility with various design tools and methodologies. Through thorough testing, identify and rectify any potential issues, guaranteeing robust runsets for the design teams.Working closely with foundries to understand process technology requirements and ensure compliance with their specifications.