Karim Syed Email and Phone Number

Technical Lead and Manager of system level testing in manufacturing. Specialty focus on board, server, and rack level testing

Lead developer for functional level testing on Annapurna's leading machine learning accelerator chips

• Post-silicon tester debug using logic analyzer tools for strobe validation and level/timing shmoo analysis. • C based test sequence writer with simulation verification using synopsys waveform analyzer (VERDI) using ASM written tests• Emulation validation execution for functional breadth and depth testing• Test plan developer and minimum test requirements/coverage definition using fault grading simulations• Wrote Perl based automation tools for pattern compilation and generation for multiple testers improving throughput time for team from 2 days to 30 minutes.• System test correlation for test hole reduction and voltage guard band optimization

Lead developer responsible for the overall standardization and architecture of test program generationto improve usability and maximize reuse. Implemented on multiple product sets.• Overhauled test program structure to leverage known industry tools to manage revision control, enable program diff, and create predictable generation model.• Defined central level and timing sequence database resulting in reduction of tester memory of 50%.• Created automated generation scripts removing dependence on non-standard tool sets resulting in reduction of test program generation from 30 minutes to 30 seconds.• Designed & implemented first automated pattern check-in process with built in error checking and revision management.

Lead developer responsible for the overall standardization and architecture of test program generationto improve usability and maximize reuse. Implemented on multiple product sets.• Overhauled test program structure to leverage known industry tools to manage revision control, enable program diff, and create predictable generation model.• Defined central level and timing sequence database resulting in reduction of tester memory of 50%.• Created automated generation scripts removing dependence on non-standard tool sets resulting in reduction of test program generation from 30 minutes to 30 seconds.• Designed & implemented first automated pattern check-in process with built in error checking and revision management.

• Atom silicon per rail power characterization and pre-silicon correlation using NETDAQ setup.• Executed performance analysis using industry benchtop tools for competitive comparison• High voltage/high temperature stress execution• Developed regression testing automation w/ perl scripts and C# written web interface

Research project on current system power usage and the effects of virtualization on hardware.