Director Soc Engineering
CurrentLeading a VLSI development team of design engineers with full HR responsibilities and technical mentorship. As resource manager responsible for the schedule of the Engineers to the different projects (matrix organization) and according to schedules of deliveries of the team.The team was responsibility for the SOC top level assembly of several SOC’s e.g Wifi SOC’s, cable DOCSIS transceiver, 2.5 Ethernet PHY next generation, 2.5G 8-port Ethernet switch, Gateway Network Processor 2nd generation.My team was additionally responsible and hosting the development of internal/external IP’s like Synopsys DDR interface (controller & PHY), ARM processor generation (A55) and integration, Arteris NOC development, integration of Security & OTP IP’s, owning power management (DVS) & PVT IP’s and the global clock & reset structure of SOC’s.
