Karthik Mohan Email & Phone Number

Redmond, Washington, Us

Deep learning model development using state-of-the-art NLP architectures. This includes data collection, curation, model training, evaluation, inference optimization, flighting & deployment of large scale models. More details about the model are as follows1) Content understanding model based on encoder-only architectures (BERT like) for tasks like article interestingness, evergreen & location-independence. These are multi-task models trained simultaneously on all these tasks and then distilled to a compressed student model meeting inference requirements.2) Personalized Neural Recommendation model ( both monolingual & universal ) built using semantic representation of documents, user profile based on historical user interaction & other contextual features. They are trained on objectives like predicting implicit user feedbacks ( click and read-time ) on news article. 3) Article summarization model based on decoder-only (GPT like) architectures for tasks like eye-catchy headline & search query generation.

Redmond, Washington, Us

1. Entity Triggering relevance (Bing Search)- built end to end data pipelines for metrics calculation and monitoring- built machine learning models using active learning approaches for ranker used in video game segment2. Data pipeline for Personalized News Recommender System - built end to end data engineering, mining, analysis, metrics and reporting pipeline using Spark, SQL & Power BI- this includes data collection, metrics computation, dashboard creation, A/B flight scorecard analysis & monitoring alerts

Armonk, New York, Ny, Us

Processor Circuit Design Engineer and Power leadDesign Implementation of L2 cache (Power 7+ and Power 8)----- End to End design flow of L2 cache. Semi-customization of timing critical paths between L2 and Load-store.Design Implementation of Test Pervasive and Power Management (Power 8 and Power9) ---- End to End design flow of unit which includes functionalities like Debug, Clock and Chip Power Management. Power leadership role for Test Pervasive and Power Management blocks ---- Restructuring RTL, synthesis optimization, logic preplacement, usage of multiVT (threshold voltage) devices and optimal routing techniques

Chennai, Tamilnadu, In

Priority queue design and implementation for RPR (Ring) topology – Summer Fellowship at IIT Madras  Monitoring and controlling traffic on a packet ring topology used in Wide Area Network Applications Simulation of the entire priority queue structure using Xilinx ISE Performed bandwidth analysis for different network workloads

Master'S Degree, Computer Science And Engineering

B.E, Electronics & Communication Engineering

Science