Karthik Ramalingam Email & Phone Number

Cupertino, California, Us

Manage wireless radio FW and RF related SW releases across all products and accessories from development phase until the product gets shipped to customers. Oversee all aspects of a portfolio which includes timelines, resource allocation and identification, scope and definition. This may include development of detailed program requirements with operations, software and hardware, finance, operations, business process re-engineering and global business intelligence teams.Manage cross-functional business and operational requirements and expectations with realistic project plans. Assist management in assessing and prioritizing projects. Perform risk management and identify solutions to overcome these risks within the project timeline.

Cupertino, California, Us

Worked on developing and validating data sync between Apple Watch, iPhone, iCloud and other related technologies. Assessed and driven improvements to the networking and connectivity software stack​. Activities include but not limited to regressions and difficult-to-reproduce bugs, write test plans, run documented and ad-hoc tests, and ensure a high-quality software experience.Coordinated with the development and performance team to both ensure full test coverage as well as to initiate focused testing on critical components for the Apple Watch.Worked on 3GPP & 3GPP2 protocol stack and SIM ToolKit to release the products worldwide. Meet carrier requirements within in the USA and the carriers outside USA.Vendor management in developing projects from the infant stage and tailoring them to match our expectations within the defined time frame.Worked with finance teams to lower the operational and capital expenditures.Worked with vendors and contractors from the US, China, Germany, Israel and the UK in negotiating deals for the purchase of hardware and software lab equipment.

Chicago, Il, Us

Worked on Integration of UE (4G Mobile) for the Public Safety LTE Division. Hands on technical experience and knowledge on LTE Protocol Stacks, OFDMA, SC-FDMA, analysis and interpretation of call flows, modulation scheme, eNB Architecture, MME architecture, SGW& PGW and the LTE end to end system design and test.Architect for the Call Processing and designed the System Test flow and documented the procedure.Radio Planning, Access planning, dimensioning and Optimization of Public Safety LTE network to trouble shoot and improve KPIs. Analysis of KPIs, investigation and improvement of network quality problems.Implementation of new RAN features, and tuning of RAN database parameters. Analysis of neighbour relations and implementation of corrections.Knowledge and practice of the RF planning tool and the measurement tools associated with it. Worked on the QoS feature compatible to the QoB features on the PSIG and the different types of application the Public Safety officials will be using.Worked on the Information Assurance feature to ensure that each Network Element in the LTE system is secure and is capable of bypassing the malignant tools and phishing. Any threats or vulnerabilities identified will be notified and will be fixed in the next release.

Chicago, Illinois, Us

Managed the LTE networks bring up at Oakland’s Glenn Dyer State Jail. This involved coordinating with the Alameda county sheriff’s office to manage the field activities and setting up demonstrations on the high speed LTE data network to the police officers and their executive management team.Worked with development and systems engineering to resolve failure cases and provide a thorough, repeatable, documented and traceable validation of the full system prior to customer delivery.

Santa Clara, California, Us

Worked in the implementation team, where I convert the Verilog RTL into gates and place and route the interconnectors for the Block and Floor Level Modules. We make sure the gates are logically equal to the original RTL; meet timing goals resolve Static Timing Analysis issues and other problems. Worked for Circuit Design/Validation Team where I was involved in the spice simulations for Flip Flops and Latches to make sure that the design meet timing and delay measurements. If not I had to adjust the sizes of transistors for the required rise and fall time and delay measurements. HSPICE tool was used and the circuits would be tested for different input conditions to obtain an optimum low to high and high to low transitions. The optimum circuits would be converted to symbols and placed in the CADENCE library for use in other digital circuits. Worked for the Validation team and wrote a script to repair data in the dual core processor which has many repairable arrays within each core. The objective of the script is to repair the faulty instructions in the dual core processor. If the core number, bit value, Macro Id, macro number and the instruction to be repaired are known then all the known values are given or else the script chooses a random value of its own and then repairs the corresponding instruction. The obtained output is then verified using a waveform tool known as DEBUSSY. If there are any garbage values then it can be easily found in the tool.

Advanced Project Management, Project Management

Msee, Electrical Engineering

Bs, Ece