Kashif Virk Email & Phone Number

Denmark

Design of ASICs/FPGAs for Communication Systems (using Verilog/SystemVerilog & UVM)

Denmark, European Union

System-Level Modeling & Design, Hardware/Software Codesign of Digital Signal Processing Systems, High-Performance Computing Systems (MPI, RDMA, PMD, DPDK, GPUDirect), System-Level ASIC/FPGA Design & Verification. 5G Mobile Communication Systems, LTE/NR Physical Layer Processing (3GPP PRACH, PUSCH, PDSCH, etc., Multi-User MIMO), Functional Splits, RAN, RU/DU Interface, Dynamic Spectrum Sharing (DSS), Carrier Aggregation, Cellular NBIoT Modeling & Architecture Design, FPGA DSP MPSoC Architectures for 5G PHY - Bandwidth Parts, Multiple Numerologies. ORAN M/C/U/S-Plane Processing. Ethernet Interface (IEEE 802.3 - PMD, PMA, PCS, MAC) IP Specification for Fiber-based Media (including RS-FEC and MACsec)

Kuwait

Associate Professor (Computer Science & Engineering)Industry-focused Curriculum Development and Implementation for the Computer Science & Engineering section and Research in Cyber-Physical Systems involving Advanced Architectures for Computer Vision, Machine Learning & Artificial Intelligence. Joint academic & industrial research activities with renowned colleagues having doctorates from the world's best Computing Science & Engineering institutions and with strong research output profiles.Startup Activities at European Innovation ForumsHigh-Performance Computing Applications in Quantum Chromodynamics (Joint Investigation of the Cluster Implementation of the Computational Model of Quark-Gluon Plasma using MPI)Designing Multiprocessor Embedded Systems (SW/HW Codesign) with ARM Cortex processors. Explorations in Embedded Neural Computing

Dublin City, County Dublin, Ireland

Hardware/Software Codesign for Cyber-Physical SoC Architectures, Multi-Core (10+) Processor Architectures for Advanced (Neuromorphic) Mobile Applications, Ultra Low Power Optimized Heterogeneous Multiprocessor SoC Designs (@ 750+ MHz Clock Frequencies and 16 nm FinFET Processes), Variable Instruction Length VLIW Vector/SIMD DSPs, RISC Processors, Coprocessors/Accelerators/Special Function Units, NoCs, etc. Verilog HDL, SystemVerilog, SystemC/C++, OpenCL, Synopsys VCS, SVN, GIT, GITLab, GNU Make, etc.Microarchitectures for Feature Detection & Vision/Deep Learning/Tensor Processing, Integration and Block-Level Verification of IP Cores.The Heterogeneous Multiprocessor SoC Architecture is a state-of-the-art processing platform for cutting-edge industrial applications as well as for carrying out research in Embedded High-Performance Computer Systems.

Linköping, Ostergotland County, Sweden

Technical Lead, Variable-Length & Multi-Issue Instruction Set Processor Architecture Modeling & Design in Synopsys IP Designer/MP Designer, C/C++/SystemC/OpenCL. Architecture Group Member, Variable Instruction Length VLIW Vector/SIMD Scalable Platform Architectures, Multi-Core, Multi-Threaded DSP Architectures, Multi-Threaded SuperScalar Architectures, Chip Multiprocessors. Team Member, SoC-based Processor Core Designs in Verilog/SystemVerilog, Synopsys VCS, XML, Python, GIT, GITLab, Jenkins, Sphinx, 28 nm & 16 nm FinFET Processes. Vector/SIMD DSP Module Design & Implementation: Permutation Units, Address Generation Units, etc. The Vector/SIMD DSP and Control Processor design at Mediatek (for cellular modems) is a generalized and scaled up version of an earlier processor design carried out at GN Resound (for audio signal processing).

Ballerup, Copenhagen Area, Denmark

Architecture & Instruction Set Co-Design. Processor Instruction Set Modeling in Architecture Description Languages (ADLs) & Processor Microarchitecture Modeling in SystemC. Design, HDL Implementation & Verification of the Microarchitectural Modules of Advanced SuperScalar Processors (Control Flow & Register/Memory Dataflow). Pipelined Instruction Scheduling and Controller Design for Pipelined Digital Systems. Low Power Cache Sub-System Design & Implementation. CISC/RISC, Princeton/Harvard, GPP/Microcontroller/DSP Architecture Design & Implementation for Embedded Computing Platforms. Exploration of VLIW, Transport-Triggered & Multiprocessor/Multi-Core Architectures & Programming Tools. Processor Design Factoring & Requirements Specification of Processor Modules. Application of Mathematical Techniques to Processor Design. High-Level Synthesis. Expertise in Horizontal & Vertical HW/SW CoDesign. Experience with Synopsys, Cadence, Mentor Graphics, Xilinx & Altera Design Environments & Familiarity with Scripting Languages. Liaisoning for HW/SW CoDevelopment. Technical Forecasting & Mentoring.

Lyngby, Copenhagen Area, Denmark

Modeling & Design of Embedded Computing Platforms with specific focus on the Modelling & Design of Networked Embedded Computer Systems (such as Embedded High-Performance Multiprocessor Systems on Chip with Networks on Chip for Wireless Integrated Sensor Networks). Mapping & Scheduling Transformations in Compilers. Research Project Supervision.

Værløse, Copenhagen Area, Denmark

RTL Design & Synthesis (for FPGAs & ASICs), VLIW Processor Core Design (in VHDL) using Synopsys (Target Compiler Technologies) Processor Core Development Tools, Intel (Altera) FPGA Design Tools, Mentor Graphics (ModelSim) & Cadence (SoC Encounter) Front End & Back End ASIC Design Tools.

Sydhavn, Copenhagen Area, Denmark

Design & Implementation of a CMOS-based Wireless Transceiver for the Bluetooth Standard(Team Member, ConFront Project)

Hasanabdal, Islamabad Area, Pakistan

Embedded Computer Systems Design & Integrated Circuit Design (Avionics)Design & Implementation of Embedded Computer Systems based on Rockwell 6502, Microchip PIC, Intel i960 Microcontrollers, Lattice CPLDs & Xilinx FPGAs, Intel i386 Control Processor & Texas Instruments TMS320C31 DSP-based System Design. ASIC Design Project Administration. Project Team Leadership.

Ph.D., Computer Science & Engineering

Activities and Societies: 15+ Research Publications (Conference, Journal & Book Chapters). Research Project Supervision.Specializations.

M.Sc., Computer Systems Engineering

Activities and Societies: Member IEEE (Denmark Section)Major: Integrated Computer Systems (Architecture & Programming) Minor: Integrated.

B.Sc., Electrical Engineering

Activities and Societies: IEEE Student Branch Chairman, University of Engineering & Technology, Lahore, PakistanMajor: Electronics (Analog.

F.Sc., Mathematics, Physics, Chemistry

Activities and Societies: Red Crescent Society, Lahore, Pakistan

Secondary (6-10), Mathematics, Physics, Chemistry, Biology

Activities and Societies: House Captain. Class MonitorMatriculation

Primary (1-5), English, Mathematics, Science

Activities and Societies: Class House LeaderPrimary