Kathy Olson Email & Phone Number

Santa Clara, California, US

Cranberry Township, Pennsylvania, US

• Tested high-level NFP flows at Fullchip SoC, with major focus on enabling PCIe and Memory Unit testing
• Enhanced Fullchip environment by defining reusable virtual interfaces, creating multiple build-time DUT configurations per repo, and implementing common command bus collateral for use at block and Fullchip levels
• Developed Memory Model for storing data from PCIe requests to Host, to enable Fullchip flows with checking
• Integrated PCIe Controller and SerDes IPs, and enabled major PCIe flows at Fullchip SoC level
• Developed PCIe testbench for MSI/MSI-X interrupt flow, and fully tested with random stimulus and coverage

Santa Clara, California, US

• Brought up OVM validation environment for address translation and memory management unit on Host-Fabric interconnect, and pathcleared major features
• Performed cross-site integration of MMU IP and SoC components for reuse efficiency
• Developed innovative TL-verilog high-level model of Fabric Switch used for end-to-end checking
• Mentored co-op to develop formal model for new Omni-Path networking protocol, which identified deadlock cases and acted as base for Fabric BFM used in dynamic stimulus on Xeon Phi

Santa Clara, California, US

• Delivered Xeon and Itanium logic design components on or ahead of schedule with first-silicon success
• Designed Xeon ring interconnect logic including crediting and ordering rules for multiple transaction classes
• Implemented and validated logic design for Message Channel interconnect, including register accesses across multiple blocks, interrupt delivery, and arbitration with off-chip requests
• Provided timely RTL fixes for pre-silicon bugs to enable project health and progress towards team deadlines

Santa Clara, California, US

• Performed pre-silicon design and validation of hardware components for 4th-generation Xeon and 3rd- and 4th-gen Itanium high-end servers
• Validated execution unit for initial out-of-order Itanium processor design including integer operations, predication, bypassing, and branch prediction
• Developed behavioral collateral including drivers, monitors, checkers, and stimulus to create and maintain validation environments in C++, System Verilog, and OVM
• Performed validation of interrupts, translation purges, sideband interfaces and exceptions to deliver functional utility logic block in Itanium server design
• Acted as team lead for two validation engineers to bring up validation environment and provide initial pathclearing of utility logic before transitioning to global validation
• Developed testplans, wrote coverage, tuned exercisers, and debugged failures to ensure thorough testing of multi-socket, multi-core, and global fullchip flows

Houston, Texas, US

• Implemented a high-level model of the Alpha branch predictor for porting across multiple architectures