Kaushik Mohan Email and Phone Number

• Process owner of chip manufacturing in CMP process (12inch SOI 14nm FEOL) involving day to day monitoring of quality, production, and path across fleet.• Created Change Point Management (CPM) report to provide statistical results with analysis. The report helped save 20 min of the user's time.• Created Down-time Monitor report to highlight root cause for tool down time (14% reduction in tool downtime).• Implemented Cost savings action projects such as slurry flow reduction, pad life extensions that reduced 20% of cost without affecting quality of product.• Reduced tool down time during Preventive Maintenance (PM) by 26% that helped improve throughput• Spearheaded quality improvement activity using FMEA and 5 Whys to determine the cause of variation in the layer. Wafer loss was mitigated from 10% to 2% of the line.• Implemented Automated process control (APC) to reduce polish time variation across pad life by analyzing root cause of standard deviation issues using Kepner Tregoe method. Variation of time over pad life was reduced by 23%• Spotlight award (2x) for teamwork and commitment to find root cause during excursion event

• Polish process owner for 4inch and 6inch SiC based wafers for LEDs and Power and RF products.• Optimized steps to determine cause for crashes on polish tool, categorized cause for crashes and implemented steps to reduce loss of wafers due to crashes. Reduced crash rate by 18%.• Reduced the polish time process of LED product by increasing capacity of tools by 2% and reduced the consumption of consumables by 9%

• Led CMP process related to 14nm technology node (Silicon On Insulation Middle of Line Tungsten Replacement Metal Gate)• Developed and tested process using Gas cluster Ionic beam (GCIB) with etch team to improve within wafer uniformity and yield by 10%• Implemented a micro-replicated pad for 14nm and 22nm MOL W RMG CMP to help improve within wafer uniformity and Chip to Chip uniformity by 12%

• Process development owner for 14nm technology node (Silicon On Insulation, Middle of Line, Tungsten Replacement Metal Gate).• Optimized the slurry composition and better blending to achieve higher selectivity (oxide to tungsten), which reduced over polish defects by 5%.• Worked on implementing post-CMP cleaning solution to reduce Foreign Materials (FM), Particulate Matter (PR), Poly scratch (PS) and etc by 10%.• Eminence & Excellence Award for leading effort on removing W CMP residuals reducing Over polish defect

My research focuses on surface characterization and novel slurry formulation for ceramic wafers. This has given me hands on experience on various characterization machines such as AFM, Malvern(Zeta potential measurement, Particle size analysis and measurement), Allied high tech bench top polisher, etc.

I learnt a great deal on how to manage time, be a responsible researcher and honing my skills such as problem solving techniques, careful examination of results, clear communication among peers and developing a healthy relationship with fellow researchers.

I did my summer internship at IITm under Prof. Abhijit P. Despande on estimating adsorption constants for BET, mBET and GAB models for PVA, PEEK, SPEEK and their blends. This was a theoretical experience as it involved understanding the fundamentals of the models and characteristics of the polymers such as adsorption, water uptake, swelling capability, etc. I continued my fourth year project under the same professor which was about rheology study of polymers under various fields.