Ajay Baranwal Email & Phone Number

California, United States

Santa Clara, California, Us

San Jose, California, Us

As Center Director I oversee projects in designing and developing deep learning products for semiconductor and electronic manufacturing. Among a range of functions I research and develop deep learning applications to drive technology innovation such as process correction, fast design construction, iterative optimization improvement, machine and system monitoring with computer vision, defect anomaly detection, and simulation environments. I also build the data and machine learning pipelines, and establish and deploy the deep learning model architectures. Additionally, I recruit and hire new staff members.A few key achievements in this role include:☛ Worked with TensorFlow Python and Keras libraries to create deep learning models.☛ Built computer vision models to design, synthesize, and convert images and create labeled data using convolution neural networks (CNNs) and recurrent neural networks (RNNs).☛ Utilized regression and classification techniques with deep neural networks, generative adversarial networks (GANs), deep anomaly detection, and Gaussian mixture models.☛ Successfully developed several deep learning-based monitoring, inspection, and predictive maintenance systems for electronic manufacturing that increased customer technology leadership and productivity.☛ Collaborated with customers to integrate deep learning models with their production systems.☛ Designed highly detailed workshops, classes, laboratories, and materials to train engineers and professionals in deep learning.

Aliso Viejo, Ca, Us

As Senior Director I led data science teams and projects in developing products for internal and external customers. Among a range of functions I provided technology direction in defining the product strategy and road-map. I also reviewed and approved technical codes, and coordinated and facilitated group architectural meetings. Additionally, I built and trained local and remote teams.A few key achievements in this role include:✪ Developed customized word and sentence embedding for natural language processing.✪ Established a comprehensive training pipeline for multiple users.✪ Built a full data and inference pipeline with servable models utilizing TFServings to enable several models for A/B testing.✪ Built a neural network-based document retrieval system with semantic document understanding featuring cognitive search and text summarization.✪ Worked extensively with natural language processing, document understanding, text summarization, and machine learning system deployment.✪ Worked on DevOps to provide virtual machines on Google Cloud and Microsoft Azure.

Canonsburg, Pa, Us

As a Technical Data Science Fellow I conducted research for machine learning application development with open-source technologies and frameworks.A few key achievements in this role include:◆ Designed a generic machine learning and neural network platform on an in-house big-database and compute engine to provide built-in customized regression modeling, analytics and prediction, and natural language understanding. Published a paper and obtained an approved patent for the system.◆ Developed several other machine learning projects for regression using TensorFlow Python.◆ Coordinated and facilitated hands-on deep learning training workshops for all engineering teams.

Canonsburg, Pa, Us

- Summary + Started Machine Learning group; researched and developed solutions of related problems by identifying right applications, go-to-market ML frameworks and applying various Machine Learning and Deep Neural Network techniques to applications. + Experience with company's state of art internal Document Based Database which enables big data, MapReduce technology to the platform and Hadoop like distributed computing using lambda architecture. + Architect for in-memory electronic connectivity database, efficient back-end infrastructure for ANSYS’ semiconductor’s flagship tools such as RedHawk and Totem in distributed computing environment. Also helped with document based database which enables big data MapReduce technology to the platform. + Cross functional interactions with Field Applications Engineers, Customers, R&D teams + Built ANSYS India R&D operation in Bangalore with continued long term technology and people management. + Strong R&D management work including hiring, training , budgeting and leading R&D engineering teams. + Worked in large scale software development life cycle, source code control using GIT, CVS, Microsoft TFS, verification, Quality of Results till final deployment to customer production releases.- Projects + Machine Learning, Deep Neural Networks technology using TensorFlow to bring learning capabilities to ANSYS products. + General purpose document based DS file system/database, distributed compute system (Similar to MongoDB & Hadoop) to run on LSFs, multi core CPUs with Python, and C++ framework. + ANSYS' Redhawk/Totem flagship products’ core infrastructure and database + Early Grid Prototype solution - architecture design, productization and deployment + In-Memory database design and architecture + Physical layout modeling (GDS/OASIS) - LVS (Layout v/s schematic) like device extraction from layout, device modeling, geometries processing.

San Jose, Ca, Us

- Database, infrastructure work for the power analysis tool- Memory/IP block modeling for static-IR/dynamic-voltage drop analysis- Layout based transistor level device extraction for power integrity requirements- Managing midsized to large R&D team- Clock tree jitter sign-off simulation- OpenAccess (EDA open source connectivity database) support

San Jose, Ca, Us

- Helped started India R&D operation- Various modeling support for EDA databases such as Milkyway, and providing layout (GDSII) modeling support

Mountain View, Ca, Us

- Integration of Blast Fusion’s C-APIs deployment with third party tools having Cadence’s OpenAccess open API interface.- Worked on Magma’s unified data model to further optimize for run time and memory footprint

Mountain View, Ca, Us

- Designed and implemented open support for Magma’s Unified Data Model- Providing C-level interface of Magma’s database with net list, timing, placement, routing information to be able to integrate with third party tools having open source EDA database interface.- OOPs, Knowledge of Logical and Physical design domains- Led team of two RDs- Got ‘Outstanding Performance Award of the year 2005.- Created detailed design and architectural level functional specs, Automation of the regression suits including creation of representative test cases, Creating release/package for the product.Interaction with multiple customers to integrate their tool using these interface.- Also, made couple trips to the customer on site to Hsin-Chu, Taiwan to interact with customers/technology partners to enable tool integration.

Cupertino, Ca, Us

- Significant contribution in preparing functional specs, designing the object-model and implementation of algorithms for Interra’s EDA objects. Also, worked on memory and run time optimization.- Managed and maintained Interra’s Netlist Object Model (database) to store connectivity information from RTL hardware design with sound flow understanding.- Wrote TCL/TK based GUI for the Schematic Viewer and also designed the internal data structure for storing CDF graph. - Extensive exposure of C/C++, lex/yacc, TCL/TK, DS, AlgoSetting up processes for bug-tracking, developing regression setup with automated scripts, run purify quantify, purecov like tools.- NOM (NetList Object Model): + Led development and support in-memory database with storage of Verilog, VHDL, EDIF logical connectivity + Managed team of 3 RDs- General Purpose Graph Viewer + A general purpose graph viewer to view schematic netlist with control flow graph.- EDA verification customer project +Creation of a verification system for customer to parse Verilog/VHDL and implement RTL design rule checks such as Gated Clocks, Combination Loops, Operator Size Mismatch, Reverse Bus Connection etc. Also worked on structural level checks. These include detection of asynchronous logic, gating of clocks etc.

Us

- Worked on the Implementation of RTL/Netlist Design Rule Checker- Automatically fixing of above DRC Violations.- Verilog/VHDL expertise

Master’S Degree, Mathematics And Scientific Computing

10+2, Physics, Chemistry, Mathematics