I am an accomplished B. Tech student in Electronics and Communication Engineering at KL University. I have garnered practical experience through internships, such as in VLSI Design and Verification at Tessolve, where I focused on digital circuit design using Verilog HDL and SystemVerilog testbench environments. As an active member of always@vlsi student club, we mentored peers and younger students, nurturing a collaborative team atmosphere and offering guidance in various tools like Xilinx Vivado, Cadence and FPGA design.