Certified as Register transfer level(RTL) VLSI Design and verification engineer.Currently as an intern in Maven silicon.VLSI design skills:1.Digital Electronics :Combinational & Sequential circuits, FSM, Memories.2.Verilog Programming :Data types, Operators, BA & NBA, Delays in Verilog, begin-end & fork- join blocks, System tasks & Functions, compiler directives, FSM coding and TB Coding with synthesis.3.Advanced Verilog & Code Coverage:Generate block, Continuous Procedural Assignments, Self-checking testbench,Named Events and Stratified Event Queue.Verification skills:1.System Verilog HVL: Memories ,Task & Function, Interface - Modport and clocking block.2.Basic and advanced object-oriented programming: Inheritance, polymorphism, copying an object.3.Constraint Randomization: constraint overriding and inheritance.4.Thread synchronization techniques: events, semaphores and Mailbox - built-in methods 5.Functional coverage: Cover groups, bins and cross-coverage, CRCDV and regression testing.6.System Verilog Assertions:Types of assertions, assertion building blocks, Sequences with different timing relationships, implication and repetition operators.7.UVM: UVM Objects & Components, UVM Factory & overriding methods,Stimulus Modelling,UVM Phases,UVMConfiguration, TLM,UVM Sequence, virtual sequence & sequencer,Introduction to RAL.