Keerthi Mahadevan Email & Phone Number

Certified as Register transfer level(RTL) VLSI Design and verification engineer.Currently as an intern in Maven silicon.VLSI design skills:1.Digital Electronics :Combinational & Sequential circuits, FSM, Memories.2.Verilog Programming :Data types, Operators, BA & NBA, Delays in Verilog, begin-end & fork- join blocks, System tasks & Functions, compiler directives, FSM coding and TB Coding with synthesis.3.Advanced Verilog & Code Coverage:Generate block, Continuous Procedural Assignments, Self-checking testbench,Named Events and Stratified Event Queue.Verification skills:1.System Verilog HVL: Memories ,Task & Function, Interface - Modport and clocking block.2.Basic and advanced object-oriented programming: Inheritance, polymorphism, copying an object.3.Constraint Randomization: constraint overriding and inheritance.4.Thread synchronization techniques: events, semaphores and Mailbox - built-in methods 5.Functional coverage: Cover groups, bins and cross-coverage, CRCDV and regression testing.6.System Verilog Assertions:Types of assertions, assertion building blocks, Sequences with different timing relationships, implication and repetition operators.7.UVM: UVM Objects & Components, UVM Factory & overriding methods,Stimulus Modelling,UVM Phases,UVMConfiguration, TLM,UVM Sequence, virtual sequence & sequencer,Introduction to RAL.

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  Trainee

  Maven Silicon

  Jun 2023 - Apr 2024 - Bengaluru, Karnataka, India

  Trained as Advance VLSI Design and Verification engineer.Have a fair knowledge on Digital electronics, verilog, system verilog, system verilog assertions and UVM. Basics of FPGA and CMOS. Worked on different projects based on above skills. Hands on experience in Linux operating system, EDA tools like Modelsim, Questasim and VCS spyglass.

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  Visvesvaraya Technological University

  Electrical, Electronics And Communications Engineering