Keith Benjamin Email & Phone Number

Minneapolis, Mn, Us

Boise, Idaho, Us

Awarded Patents:US11921647US12019912

Norfolk, Va, Us

- Initial qualification pipeline.- Provide technical leadership and program management of naval repair efforts at US naval shipyards.- Lead and manage local reserve community workforce in completion of US Navy wartime readiness goals to include technical proficiency, qualification completeness, and physical fitness.

St. Paul , Mn , Us

- Lead the company's first ISO9001 and AS9100 certification for five functional groups.- Lead the development of an Advanced eXtensible Interface (AXI) interconnect and custom internal protocoltransaction layer enabling streamlined internal Intellectual Property (IP) reuse.- Designs the Sideband components for a Universal Chiplet Interconnect Express (UCIe) version 1.1 IntellectualProperty (IP).- Provided schematic fault and design analysis expertise for an external customer identifying three possible corrective actions.

Boise, Idaho, Us

- Promoted from Engineer Grade 3 to Engineer Grade 4 effective 05 Nov 2022.- Designed channel shaping and control algorithms for next generation Universal Flash Storage (UFS) physical interface MIPI M-PHY6.- Modeled the M-PHY6 digital-to-analog communication channel for PAM4 and NRZ signal regimes for exploratory control designs and final validation.- Developed metrics for end-to-end simulation-to-silicon correlation for pre-manufacturing design verification and post-manufacturing validation.Awarded Patents:US11514995US11544203

Boise, Idaho, Us

- Reduced program testing cost by implementing a full-rate on-die logic analyzer for internal signal validation reducing expensive eternal test equipment requirements and enhancing test automation.- Designed and validation experience in UFS 5.0, MIPI M-PHY 5.0, and MIPI UniPro 1.8 ASIC designs.- Designed and implemented an 80-bit ASIC Pseudo-random Binary Sequencer (PRBS) capable of running up to 132Gbps while reducing power consumption 9.3% and area requirements 2.5%.- Spearheaded the static analysis and clock-domain-crossing (CDC) effort for two test-chips leading to on-time tape-out.- Designed and implemented a 23Gbps on-die logic analyzer for in-situ bus monitoring, data capture, and fault analysis.- Led the design team to an on-time validation a new ASIC design.Awarded Patents:US11353942Published Papers:"Pseudo-random binary sequencer minimalization" [Mar2021]

Boise, Idaho, Us

- Promoted from Engineer Grade 2 to Engineer Grade 3. Effective 03 Nov 2019.- Create and maintain firmware in support of Non-Volatile DIMM (NVDIMM) applications.- Implement security measures for low-level device hardening.- Implement JESD245B.01, the JEDEC Byte Addressable Energy Backed Interface (BAEBI) standard.- Maintain system level Python integration tests.- Redesign hardware implementation where necessary.- Implemented and maintained NOR and NAND Flash-Translation-Layer (FTL).- Implemented and supported Xilinx Microblaze on FPGA enabled applications.- Redesigned board level Power Delivery Network (PDN) to mitigate existing design flaws which prevented full acceptance test completion.- Submitted four patents as the principal inventor and two patents as a supporting inventor.Awarded PatentsUS10877541US10984881

Norfolk, Va, Us

- Collaborated with an interdisciplinary team of aerospace, mechanical, and electrical engineers to develop an Adaptive Fuzzy Logic controller for a Model-Less Aircraft.- Demonstrated 1-DOF (Degree-of-Freedom) control of an unknown system in NASA’s low-speed wind tunnel in order to support aircraft system identification without the need for Computational Fluid Dynamic (CFD) models.

Williamsburg, Va, Us

- Designed and implemented avionics hardware for safety-critical weapons control and release applications.- Implemented initial DO-254 standards programs.- Member of the Safety Review Board as the principle Electrical and Computer Engineer.- Implemented systems using Altera products utilizing the Quartus II toolset with VHDL- Designed high speed digital hardware for USB 3.1 and 1Gbps Ethernet.- Embedded development of 32-bit Real-Time Operating System (RTOS).

- Evaluated project Science and Technology (S&T) development for future military applications.- Managed the acquisition life-cycle for Future Vertical Lift (FVL) and related technologies.- Rotorcraft Advanced Engine Integrated Control Systems (RAEICS) technology maturation program management team member.

Lanham, Md, Us

- Conducted earth science research in conjunction with the Albemarle-Pamlico National Estuary Partnership.- Utilized AQUA satellite’s MODIS sensor data to track the range and extent of Harmful Algal Blooms (HAB) in North Carolina’s Albemarle and Pamlico Sounds.- Validated AQUA MODIS measurements with in-situ data to determine the feasibility of HAB tracking using AQUA MODIS, the OC3M processing algorithm, and the SeaDAS software package over in-land waterways with high turbidity.

Washington, Dc, Us

- Directly managed eight personnel in the repair of the F-18 Variable Speed Constant Frequency (VSCF) generator produced by General Electric with a certified repair rate of 98 percent.- Implemented LEAN/Six Sigma practices in training, inventory management, and repair practices which increased work center efficiency 85 percent and resulted in a cost savings of $62M.- Established the benchmark by which all deployable generator work centers are measured for repair rate and cost avoidance.- Maintained a Secret security clearance.

- Designed and installed small to medium scale computer networks.- Administered networks using Windows server and Linux distribution variants.- Cisco Certified Network Associate (CCNA) [April 2002 – April 2005]

Master Of Engineering - Meng, Engineering Management

Master’S Degree, Electrical And Computer Engineering

Bachelor’S Degree, Computer Engineering