Keith Painter Email & Phone Number

South Burlington, Vt, Us

Essex Junction, Vermont

Product Engineering and System Characterization for IBM Z and P server processors.

Williston, Vt

Test Development and hardware characterization for ASICs and embedded memories (SRAM, TCAM, ROM, and more) and other associated circuit components, such as eFuse.Responsibilities include:* Creating, maintaining, and modifying Perl, SAS, and R scripts to aggregate, organize, and modify large volumes of data.* Using R, SAS, Excel, and Perl to perform statistical and visual analysis of those large data sets.* Create, maintain, and execute hardware qualification plans, including follow up with full qualification results and analysis

Williston, Vt

Test Development Support contract position with Global Foundries working on hardware characterization for ASICs and embedded memories (SRAM, TCAM, ROM, and more).Responsibilities include:* Creating, maintaining, and modifying Perl, SAS, and R scripts to aggregate, organize, and modify large volumes of data.* Using R, SAS, Excel, and Perl to perform statistical and visual analysis of those large data sets.* Create, maintain, and execute hardware qualification plans, including follow up with full qualification results and analysis

South Burlington, Vt

Manual test and automated test development using the Agile software development methodologyCreated back end automated testing platform using C# and built in Windows screen object recognition capabilities.Create and maintain manual test plans, both for individual user stories and top level epicsIdentify and document bugsManual testing across multiple platforms (Windows 7, Windows 8, Citrix) with multiple browsers (IE8, IE9, IE11)Assist developers in software debugging and fix implementation, including code recommendations and rapid turnaround sandbox testing

Williston, Vt

Test and software engineer for Phase Change Memory research and developmentResponsibilities include:Test plan developmentC++ test code development and deployment for Nextest Magnum 2 testersNew product mapping and problem troubleshooting on Electroglas 4090 and 4090u probersPerl code development for data aggregation and post processingDesign For Test requirements and improvementsLab equipment maintenance and repairPhysical design for experimental circuits

Burlington, Vermont Area

Low Power and Commodity DRAM design (LPSDR, LPDDR, LPDDR2, DDR2, and DDR3), with responsibilities including spice simulation (fullchip and block level), verilog simulation and environment development, circuit design, physical design, and script development.

Burlington, Vermont Area

ASIC library timing characterization and modeling, with responsibilities including pattern creation, timing rule definitions, creating timing equations to fit characterized data, software creation and debug, customer support, and documentation, with a small amount of circuit design.