Keith Joyce Email & Phone Number

Raleigh, Nc, Us

Raleigh, Nc, Us

Falls Church, Va, Us

Falls Church, Va, Us

Led a team of 10 verification engineers in a complex effort involving both subsystem-level and block level UVM verification environments, JasperGold connectivity, Cadence Interconnect Workbench (IWB) verification, and SystemVerilog Assertions (SVA).

Williston, Vt, Us

Williston, Vt, Us

Contributed to the verification of multiple High-Speed SerDes designs using System Verilog in a UVM environment. Developed agents (driver/monitor/sequence/interface) and tests for multiple calibration modules. Led the code and functional coverage reporting effort using Cadence vManager/eManager.Contributed to the design (Verilog), verification and customer support of DDR3/4 PHY core. Coordinated with design and verification (System Verilog) teams in the analysis and debug of customer simulation (Synopsys, Cadence) / hardware issues. Developed Perl scripts to facilitate analysis.

Sunnyvale, Ca, Us

Silicon validation -- developed testcases (Perl), utilized various OTN/SONET test equipment (JDSU/Anritsu) to verify hardware functionality of 40G OTN/SONET/Ethernet Optical Transport Processor

Sunnyvale, Ca, Us

Advanced verification - developed testcases, reference models/scoreboards to verify subsystems of 40G OTN/SONET/Ethernet Optical Transport Processor using Open Vera, Verilog.

■ Managed the CPU and Peripherals team for the access subsystem of a WCDMA/GPRS/EDGE compliant digital baseband ASIC. ■ Directed the effort of the team of ten engineers in developing the backplane and peripheral blocks, while also supporting the AXI subsystem and AHB bus matrix development and Specman-based verification. ■ Led the investigation into the backplane architecture for Ericsson's next generation baseband digital ASIC. Investigated the use of network on chip implementations including the Arteris NoC Solution. ■ Formulated project plan for future backplane architectural development - methodology involved system modeling (performance analysis and validation), integration, verification, and ASIC front end physical synthesis development.Managed company transition from an AHB-based architecture to AXI-based architecture. ■ Configured, integrated and verified the AXI subsystem, AXI protocol bridge cores, and AHB bus matrix for an AMBA 3 AXI-based architecture. Utilized Cadence Specman and vManager for verification of AXI subsystem and AHB bus matrix. Provided AXI subsystem analysis and insight for several additional ASIC projects across multinational organization. Supervised and mentored junior engineers. ■ Handled the digital ASIC block release flow for the Application CPU subsystem and external memory interface controller (3rd party IPs) and developed the verification environment for the application subsystem of an EDGE-based digital baseband ASIC that entailed both an AHB bus emulator model and a DSM model of an ARM926.

■ Contributed block development (design, verification, synthesis), system simulation, and DFT support for numerous digital baseband ASIC projects. ■ Generated the boundary scan logic for a GPRS compliant digital baseband ASIC. Utilized Mentor's BSDArchitect to generate the top level architecture of the chip and the IEEE 1149.1a compliant TAP controller and associated registers for JTAG level testing. Designed the block that controlled the mission mode and test multiplexing for the top level pins. ■ Designed the digital receiver for a combined IS-136 and GSM compliant chipset. Used a combination of Agilent's ADS, Matlab, and Specman to verify the design for an ASIC implementation. Implemented and verified the design in a Xilinx FPGA. ■ Developed a complete EDGE receiver simulation model of the designed RF, digital baseband, and DSP solution using Agilent's ADS. Employed the Agilent ADS EDGE Library to incorporate source and sink components to evaluate BER and BLER performance for various EDGE MCS scenarios providing the basis for trade-off analysis.■ Coordinated with DSP engineer to implement the automatic frequency control algorithm for a first generation WCDMA compliant digital ASIC. Directed floating- to fixed-point conversion for simulation models (COSSAP).

Supplied block development and verification support for several baseband digital ASIC implementations. Designed the timing block for an IS-95 compliant digital ASIC. Simulated and verified the timing block and a Viterbi decoder in a top level ASIC implementation and on an Altera FLEX FPGA-based prototyping platform. Verified various digital ASIC modules for an IS-136 compliant digital ASIC.

Falls Church, Va, Us

■ Designed and analyzed various wide area networking options for the Tribune News Photo Archiving System■ Coordinated the development of a test network for the Office of Scientific and Weapons Research (OSWR) VISTA project. ■ Designed communications plan for U.S. Air Force Civilian Personnel Records Management System (CAPRS) Integration Requirements Specification. Recommended communications alternatives and communications hardware and software necessary for file transfer over the Defense Data Network.■ Assisted in the development of a comprehensive executive information system (EIS) for the Defense Production Logistics Data Center (DPLDC) using Pilot Lightship and Oracle RDBMS.

M.S., Electrical Engineering

B.S., Electrical Engineering