Keith Spencer Email & Phone Number

Boise, Id, Us

Santa Clara, California, Us

Defined system architecture and designed FPGA board level test infrastructure for automated testing of Quartus software outputs validated in FPGAs.Managed design, manufacturing, and deployment of low volume FPGA test hardware, peripherals, add-in cards. and board level FPGA programming solutions. Completed over 35 PCB projects for Agilex, Arria, Stratix, MAX series FPGAs, rack test infrastructure, programming solutions, and designs of experiment(DOE).Maintained a hardware lab hosting datacenter rack mounted FPGA test boards for global user access including server and networking infrastructure for access and scheduling.Performed 3D CAD modeling of board and component assemblies for mechanical design and component placement.

Developed design examples, tutorials, and web content for video/image processing applications

Defined feature enhancements for Quartus design tools to improve customer design experience using FPGAs.Authored and presented internal technical symposium material to educate stakeholders on advanced FPGA topics and design issues to promote corrective actions or enhancements.

Served as product manager interfacing with global customers by hosting detailed design reviews of FPGA projects in order to approve for design conversion.Managed over 120 Stratix FPGA to HardCopy structured-ASIC customer design conversions (130nm to 40nm) to product approval for volume manufacturing.

Resolved escalated FPGA design tools issues for top tier customers.Wrote technical documentation to improve customer design experience using FPGAs.Authored and presented training material to internal and external stakeholders.

Centennial, Colorado, Us

ASIC Design Services for standard cell ASICs. Synthesis, Static Timing Analysis, Place & Route, Physical Layout, Physical Layout DRC, Test Insertion, Manufacturing Test Program Debug.Completed over 12 standard cell ASIC designs (0.35µm) for customers by executing some or all stages of the RTL to GDS2 ASIC design flow steps on these projects.

Ca

Engineering Internship.Qualified and implemented JTAG test flow development and manufacturing debug process

Bs, Electrical Engineering

Master Of Business Administration - Mba