- Leading the development of Intel’s high-bandwidth package and socket technologies for emerging high-speed on- and off-package interfaces such as 224G SerDes, UCIe, etc. - Also responsible for development of corresponding modeling & characterization methodologies and collaterals for multiple generations of these technologies.- Key contributor in industry-first technologies such as EMIB, low-loss package and socket technologies for PCIe and DDR, and top-side interconnect for high-speed Fabric.- Expert in high speed interfaces, signal integrity, semiconductor packaging, and electromagnetic simulations with a PhD in Computational Electromagnetics from UIUC.- Co-author of 5 book chapters, > 100 journal and conference papers, and 174 granted patents. For full list of publications and patents, please see: https://scholar.google.com/citations?hl=en&user=n89j2LAAAAAJ- Awarded as an IEEE fellow, class of 2022, for “contributions to high-bandwidth and high-speed packaging and socket technologies.”