Kendall Mccord Email & Phone Number

Garland, TX, US

Richardson, Texas, US

• Define, architect and develop DFT and test solutions
• Cadence Encounter/Modus Test ATPG
• Test Synthesis with Genus Stylus UI
• Incisive/Xcelium GLS simulations
• Programmable Memory Built-In Self-Test (PMBIST)
• Hierarchical Test using IJTAG (IEEE 1687), scan insertion, bounding, pattern generation

Richardson, Texas, US

• Automatic Test Pattern Generation (ATPG) using:
• Mentor Graphics Tessent Shell for IJTAG cores (IEEE P1687)
• Cadence Encounter Test for Fullscan and Compression ATPG
• Verification and simulations with VCS and Verdi debug
• Test vector translation from STIL to V93000 ATE
• IDDQ test bring-up support on 93K tester

• Provided product test planning and documentation. Validated system HW/firmware in lab. Developed, debugged and executed complex software and hardware test solutions.
• Defined production test plans, assessed coverage, and documented test methods.
• Validated ATPG tests on prototypes with pattern generator+logic analyzer prior to ATE readiness.
• Automated lab equipment, wrote drivers & programmed flash using Python, I2C, SPI, and USB controllers.

Dallas, TX, US

• Defined production ATE test plans & methods for multicore OMAP SoC designs with low power, high performance, ARM-Cortex, DSP, LPDDR, camera, display, USB, HDMI, graphics, and adaptive voltage scaling power management.
• Managed smartphone application processor test projects (OMAP4430, OMAP3430, OMAP2430, OMAP2420) with worldwide DFT teams, defining test plans and setting silicon debug priorities.
• Collected, analyzed, and reported device split lot characterization data across multiple foundry wafer fabs using PERL, SAS, and Spotfire SW. Highlighted parameters that needed to be relaxed with customer agreement and.
• Performed extensive debug in the lab and on the ATE to identify design issues with ESD, latchup, and CPU performance, and then verified the design fixes before product release.

Dallas, TX, US

• Supervised team of engineers creating test strategies for OMAP and wireless connectivity (Bluetooth, GPS, Wi-Fi, WiMAX) devices with the charter of improving test quality and reducing test costs.
• After performing production test cost analysis for on OMAP product in development, convinced management to include TestKompress ATPG compression logic, which reduced test time by 30% and saved $5,000,000 over its.
• Defined new test methods for active/standby leakage reduction logic and demonstrated working code on an early silicon test chip with 30% reduction in test time for capture of on-die performance circuits. Created the.
• Mentored and trained junior engineers one-on-one, through organized group brown bag sharing sessions, and presentations at the annual TI Symposium on Test.

Dallas, TX, US

• Developed test architectures and tools for C55X DSP subsystems. Created functional tests written in assembly for verification and validation using Verilog, ModelSim, Signalscan, and Code Composer tools. Performed.
• Involved in all aspects of new product development for C5510 DSP including: DFT, test HW design, test vector generation, test program development, first Si wafer probe/debug, and support of qual & ramp to production.
• Developed software processing flow to convert existing serial load test vectors to parallel load method, resulting in test-time reduction of 70%.
• Maintained and released the reusable test vector suite for C54X DSP core used throughout TI.

Dallas, TX, US

• Worked in all aspects of new ATM & DSL networking ASIC development including: DFT, PCB design, test vector generation, ATE program development, wafer probe, debug, characterization, failure analysis, qualification, and.
• Expanded the PE role to include functional & ATPG test vector generation and Verilog testbench simulations. This freed design resources and improved understanding of the device operation and manufacturing test.
• Characterization and analysis on the ATE established the final product datasheet parameters and confirmed customer spec compliance.
• Successfully released to production ATM & DSL (Amati Communications) networking devices by interfacing with customers (Sun Microsystems), design, packaging, and applications functions.

Bachelor Of Science (Bs), Electrical Engineering (Bsee)

Associate Of Science (A.S.), Pre-Engineering