Director of Special Projects, VCSEL R&D, Princeton Optronics, Inc.- I was the lead interface between VCSEL R&D, customers, marketing, module development, and manufacturing.- Coordinator and author of RFI/RFQ responses and driver of sample deliveries for key customers and technologies.- I worked with our module and marketing teams to demonstrate viability and benefits of a new 1130nm VCSEL wavelength for behind OLED proximity modules with good performance and <1% screen distortion, in addition to other applications.CMP Lead for Planar Optics Development, Ang Mo Kio, Singapore (Special Project Request by Upper Management based on my IBM CMP Experience)- Drove grinding, lapping, and polishing process, pad, slurry, filtration, and carrier/jig design improvements to meet customer specifications for flatness, roughness, defectivity, bond-line recess with balanced polish removal for the opposite sides of a complex periscope optic.

- I led a team of approximately 20 scientists and engineers to develop, qualify, and release into mass production LED-based automotive turn indicator, daylight running lights, and headlight modules. - Executed automotive NPI and reliability processes.- Transferred manufacturing and ongoing reliability testing capability to Cree’s factory in China. - Worked closely with manufacturing to ensure that all processes and controls were automotive ready to successfully pass the automotive customer audits. - Key developments included redevelopment of AuSn die attach metallurgy, resolution of panel corrosion and die attach issues, and development of a new TSV (surge protector) design and supplier.

- I led a team of approximately 20 R&D engineers and scientists on InGaN and AlInGaP die development programs for Automotive, Flash, Illumination, and Display product platforms. - My team and I worked with design, process, EPI, and product development teams to ensure a strong product portfolio: improved thin film flip-chip blue/white LEDs to industry leading light output efficiency; increased high current reliability performance of chip-scale-package blue/white LED die to 350mA/mm2 for automotive applications; and improved red LED light output and reliability performance to competitive benchmarks.

- Co-developed and industrialized three generations of Lumiled’s first flip-chip CSP die for multiple generations of phone flash modules, UV LEDs, and Pixelated Headlights.- Ensured seamless integration of CSP processes into the Singapore wafer-fab and die-fab and ensured alignment with EPI R&D in San Jose; L1/L2 processes in Penang, Malaysia; and multiple vendors.

- I revised IBM’s NPI methodology based on learning from the Chartered technology transfer project. - Educated and drove R&D and manufacturing teams to meet new NPI metrics for developing manufacturing-ready technologies for both 45 and 32nm technology nodes.- Led the technology transfer of 32nm SOI with high-K gates and embedded eDRAM to Global Foundries' teams in Malta, NY, USA and Dresden, Germany.

- 300mm back-end and far back-end of line (BEOL & FBEOL) lead for 90nm technology transfer from IBM to Chartered Semiconductor the XBox 360 CPU.- Advised on tool selection and drove integration/process-output matching to help take Chartered Semiconductor (now Global Foundries) Fab 7 from a shell to qualification and manufacturing ramp. - Key contributor in diagnosing and solving challenging yield issues including a device clock issue.- Added middle-of-line (MOL) lead and front-end-of-line backup to BEOL responsibilities for 65nm.- Met every qualification, yield, and customer shipment target on time for both 90 and 65nm CPUs.

Manager 300mm Cu CMP ----- Jul 2023 - Jun 2004- I led a taskforce and managed the process team to get 300mm Cu CMP back to 200mm capability and stability.Manager CMP & CVD/Spin-on Insulator Process Dev. Engineering ----- Jul 2001 – Jun 2003 - Managed CMP & insulator deposition process development teams (approximately 20 engineers).- Guided Poly-Si CMP & W CMP to similar process stability as Oxide, STI & Cu-CMP. - Led the insulator team through the difficult and high pressure down selection between spin-on and CVD-based low-k dielectric paths for IBM’s first low-k dielectric manufacturing release. Cu, Oxide, STI & Poly-Si CMP Process Development Engineer ----- Sep 1996 – Jun 2001- I started as the Oxide CMP lead and gradually worked on every process except for W-CMP.- Reduced scratching by 10x For STI & Oxide CMP.- Modified CMP carrier/jig design on outdated polishers to improve polish uniformity to match that of cutting-edge active-carrier polishers for a cost of less than $5k tool.- Worked with consumable manufacturers to incorporate the CMP carrier modifications into a consumable film to allow us to transfer the uniformity improvement to manufacturing fabs.- Took Cu CMP for IBM’s industry-leading interconnect BEOL from an unstable process (cleaning issues, pad variability, slurry particle instability, and immature understanding of the chemistry interactions with the process) to a stable, manufacturable process and transferred all learning to manufacturing.