Principal Engineer
Post Silicon Verification for a several generations of System on a Chip (SOC) devices, ranging from 6 to over over 30 Cores, targeting the 5G and server markets.- Primary job responsibility involves the use of the linux environment to deploy varied suites of stress tools to heavily exercise chips for the purpose of detecting Silicon, Kernel and driver bugs. Primary focus was on testing the network interfaces of these SOCs through the use of linux based networking applications. Driving mixed traffic loads into the device using a Xena Traffic Generator at all speeds the particular SOC supported on all interfaces, typically 1G through 400G rates. Special focus on IPSec and macsec feature testing.- Testing designed to utilize whatever applications would be supported by our Kernel in field be it ODP or DPDK and always linux network device driver approaches (netdev). Each application would exercise the internal hardware features in unique ways.- Architected test techniques, testbeds, strategies as necessary to verify new SOC hardware accelerator features as they were added to the products, for example Inline IPSec and macsec required innovative testbed setups. - All testing performed by creating traffic generation/verification loops that run at line rate for all supported protocols (speeds). Traffic generated at Xena, looped through one or more ports of the SOC/Xena and then verified back at the Xena. Goal is to always provide a Xena / Unit Under Test standalone test bed, but in some instances, as was the case with macsec, the addition of a switch was necessary to create a complete and verifiable encrypt / decrypt traffic loop. - Testing designed to stress as many of the internal SOC hardware blocks, and with as much variance that these basic DPDK sample applications could provide: NIC Hdwr blocks, Serdes, Phy, Encryption, Decryption, various types of work scheduling, various NIC Caches, CAMs, a variety of cut-through or fast paths.
