Helping chip designers achieve their Functional Safety goals

Helping to make Visualizer(tm) the best-in-class EDA debug environment.

Supported development of multiple high-performance SPARC processor chips by designing, implementing and supporting software tools/flows for the RTL design and verification teams, working closely with the users.The largest tool (45K+ lines of Perl/OOP) manages sets of thousands of jobs running in an on-premise PaaS cloud of 15K CPUs, recording pass/fail results and job statistics (e.g., memory usage) in a MySQL DB, and making results available on the internal web in real time via Perl/CGI and PHP. Statistics on memory usage and job run time are used to optimize memory requests and turnaround time for future runs.Designed and supported a continuous integration tool (10K lines) that uses the first tool to test design changes before release, and this requires extensive interaction with the in-house code versioning management system. Developed numerous other tools/flows. Ported tools from Solaris to Linux. Documented all tools using TWiki and responded to user requests. Used Perl (including OOP and CGI), MySQL, PHP, Bugzilla, HTML, Linux, Solaris, GNU Make, RCS.

Worked on multiple SPARC processor chips doing RTL design verification. Primary owner of the programmer's reference manual for one chip. Developed/documented several key elements of the verification methodology.

Design and implementation of commercially-available high performance cycle-based Verilog logic simulator in C++

Design and implementation of commercially-available high performance cycle-based Verilog logic simulator in C++. Company was acquired by Avant!

Key designer and implementer of RapidSIM and the Logic Workbench Simulation Backplane in C++ (300K lines), including synchronization algorithm, simulator API, results file format, command interpreter, and event-driven interprocess communication.

Key designer and implementer of RapidSIM and the Logic Workbench Simulation Backplane in C++ (300K lines), including synchronization algorithm, simulator API, results file format, command interpreter, and event-driven interprocess communication. Company acquired by Cadence Design Systems.