Kenny Ly Email & Phone Number

Carlsbad, California, US

• Set up manufacturing test flows by defining test limits, analyzing test coverage, performing root cause yield analysis, and ensuring performance compliance
• Evaluated chip electrical performance using Advantest 93K tester and in-house proprietary GS111 bench instruments
• Collaborated with custom package suppliers (substrates, graphite sheet & lids), and chip assembly vendor (Fabrinet) to improve manufacturing processes and reduce costs
• Supported the chemistry teams in building chips with polymer & sugar coating, coordinate the electrical testing of the assembled chips, analyze the test data, and provide the functional chips for DNA sequence testing
• Hands on support for product reliability qualification by defining qualification plan, developing hardware design, verifying qualification conditions, and performing data analysis
• Managed chip supplier chain, assembly build forecast, ATE test arrangement with local vendor, and chip inventory to ensure no shortage of chips for DNA sequence testing

Carlsbad, California, US

• Managed and led 2nd source lead-frame & substrate qualifications to increase assembly capacity to support customer shipments for QFN (88L 10x10mm/48L 7x7mm) and FBGA (31x31mm/33x33mm) packages
• Owned products from inception to production release including product bring up, characterization and qualification. Presented product schedule and update with cross-functional teams
• Conducted new product and package qualifications (HTOL, ESD/LU, HAST, TC, HTS) for highly integrated PAM4 DSP devices
• Performed product characterization, data analysis including determining test limits for all test programs, and ensure test coverage is consistent with test plan documents prior to production release
• Supported cost reduction activities including material change qualifications, test time reduction and yield improvements. Managed customer product complaints (RMA) and drove resolution closure

San Jose, California, US

• Standardized the package for high-speed TIA bare die qualification to one QFN package leading to cost saving of $200K per qualification in ATE test/qualification hardware as well as reducing time to market
• Defined qualification plan and hardware requirements (HTOL boards, HAST boards, ESD, LU) and worked with subcon vendors to procure and the design of the required qualification hardware
• Managed qualification vendors and subcontractors, and drove the execution of qualification tests (HTOL, ESD, LU, TC, BHAST, HTS), and published internal and external customer facing qualification reports
• Conducted on-going reliability monitoring test (ORM) and support failure analysis and RMA from customers

Palo Alto, California, US

• Recognized with ‘Spot Award’ for the execution of 28nm HTOL and detection of Fab defect caused by missing DRC check related to “high voltage poly resistor to P+ dummy OD” spacing. This task saved company millions of.
• Ownership of products from cradle to grave, and released multiple DSL products to production which brought in $15M to $20M of revenue per quarter
• Generated qualification plans and coordinated with external vendors to execute qualification tests (HTOL, ESD, Latch-up, Temp Cycle, Thermal Shock, PCT, HAST, HTS)
• Analyzed HTOL data and published shift analysis reports to QA/Rel group for approval/sign off
• Performed split lot characterization to ensure product has sufficient margin over voltage and temperature across fab process window
• Supported RMA activities to verify customer issues, identified root cause and implemented corrective actions

San Jose, CA, US

• Drove acceptance of manufacturing changes (PCNs) for gold wire reduction and QFN Saw migration leading to annualized cost savings of $2M
• Increased production capacity and capability by qualifying new vendors for wafer sort, assembly and final test
• Managed quality metrics to eliminate defects and implemented 8D problem solving methodology
• Improved business process and best practices by streamlining & engaging customers in the conversion process

San Jose, CA, US

• Managed seven product engineers in qualifying new and existing products for Automotive market
• Improved 10X reduction in defect level by enhancing manufacturing flows with burn-in & temperature testing
• Increased product offerings by qualifying fifteen based products to the Automotive Qualification Standard (AECQ100) with production part approval documentation (PPAP)
• Managed internal and external customer conference calls to address customer requirements on product roadmap and future plans

San Jose, CA, US

• Performed product validation and characterization tests using bench set up and automated test equipment (ATE) over temperature and voltages
• Executed process, package and product qualification tests (Op Life, HAST, Temp Cycle, Autoclave, ESD/LU)
• Implemented test time reduction and test insert reduction to reduce costs for wafer sort and packaged level test
• Interfaced with foundry partners (TSMC, Charter), design, test, quality to resolve process and product issue

• Led new product development team to develop and deliver clock products to market
• Qualified and released ~ 50 CMOS and BICMOS clock products
• Performed characterization tests using bench setup and Sentry tester to verify product performance to specifications

• Led new product development team to develop and deliver mixed signal audio and video amplifiers
• Awarded “Product Innovation” plaque for leading team to deliver the lowest noise “Boomer” audio amplifiers
• Performed characterization tests using LTX/Teradyne testers to validate product performance to specifications