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- 20+ year experiences of high speed signal related projects in board/chip level, industry and consumer area.- SerDes Validate Engineer: Expertise and Extensive experience in SerDes and SerDes related project. Understand well SerDes architecture and its building blocks and validate these blocks: such as PLL, TXPLL, Tx FFE, Rx CTLE/DFE, CDR and validate SerDes Evaluation and Characterization for different standards: Gigabit Ethernet, OIF CEI, PCIe, Fiber Channel, Serial ATA, SAS, Infiniband, RIO, DP, MIPI,USB.- SI Validation Engineer: Strong Background in High-Speed Signal Integrity Analysis, transmission lines, impedance matching network, electromagnetics, TDR, VNA testing, passive channel analysis, de-embedded, equalization and Jitter Analysis.- System Design Engineer: optical transponder, high speed backplane, SerDes evaluation board from schematic design to board stark up/layout, transmission line layout, power integrity analysis, signal integrity, noise filter built etc.- Expert in Analog-Mixed Signal Lab: Jitter Test and Analysis: Dj (ISI+CDC), Rj, TDR, VNA , Spectrum Analysis, Phase Noise, Sampling Scope, Real Time Scope , VNA, JBERT, BertScope , SSA(PLL Phase Noise +VCO analysis), TDR. Lab automation, LabView, Python.
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Principal Hardware EngineerApple Dec 2012 - PresentCupertino, California, UsWork on high speed analog mixed signal (AMS) project in AMS lab. -
Principal Engineer/ManagerInphi Corporation Aug 2012 - Dec 2012San Jose, California, UsValidate 28Gbps SerDes: TxPLL, Phase Noise, Tx Jitter analysis, Rx CDR, CTLE, DFE, Jitter Tolerance, VNA, TDR. -
Principal Engineer/Senior ManagerHuawei Nov 2010 - Aug 2012Shenzhen, Guangdong, CnSelect,Analyze and Validate SerDes IP from Vendor in North America from low end (1Gbps) to high end (25Gbps). Build up and run SerDes test labs in China and US. Evaluate the performance of SerDes IP in Huawei's system. Guide the PCB trace/channel SI and PI for SerDes application. -
Sr. Staff EngineerXilinx Oct 2008 - Nov 2010San Jose, Ca, UsValidate SerDes, Tx with Jitter analysis, TxPLL analysis, De-emph, Rx CDR test, Jitter Transfer Function for PLL and CDR, CTLE, DFE. PLL/VCO phase noise. Jitter Tolerance Test,TDR, VNA. High Speed trace layout. Signal integrity, Power integrity. -
Principal EngineerLsi Corporation Nov 2001 - Oct 2008San Jose, Ca, UsDesign high speed SerDes Eval board: circuit design, stack up, layout, signal integrity analysis, transmission line analysis, TDR,TDT, VNA. Evaluate SerDes, Tx with Jitter analysis, TxPLL analysis, De-emph, Rx CDR test, Jitter Transfer Function for PLL and CDR, CTLE, DFE. Evaluate on-die thermal sensor. Automation LabView, Python -
Sr.Staff EngineerAmcc Jan 2000 - Nov 2001Santa Clara, Ca, UsDesign Evaluation Board for SerDes OC-48(2.5Gbps), NP(network processor) -
Senior EngineerNortel Networks 1993 - 2000CaSystem/board Design: T1/E1, Sonet, OC-3, OC-12, OC-48(2.5Gbps), OC-192(10Gbps), Access, Transportation, Optical-Electric.
Kerry Hu Skills
Frequently Asked Questions about Kerry Hu
What company does Kerry Hu work for?
Kerry Hu works for Apple
What is Kerry Hu's role at the current company?
Kerry Hu's current role is Principal Hardware Engineer at Apple.
What is Kerry Hu's email address?
Kerry Hu's email address is li****@****hoo.com
What skills is Kerry Hu known for?
Kerry Hu has skills like Serdes, Signal Integrity, Asic, Pcie, Soc, Pll, Debugging, Mixed Signal, Semiconductors, Ic, Analog, Cmos.
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