Principal Engineer
CurrentFully developed and prototyped Pixel IPs on Xilinx UltraScale+ MPSoC and Altera SoC FPGA• Successfully delivered over 8 pixel RTL IPs by translating from C/C++, MATLAB, and Simulink models to micro-architecture design, test bench development, RTL coding, assertion implementation, functional coverage analysis, formality equivalence checking, Spyglass linting, synthesis, FPGA prototyping, thorough documentation, and integration support for mass production.Fully developed and prototyped high Speed, long Reach Serial Interfaces on Xilinx Virtex-7 FPGAs• Defined and implemented an intra-panel high speed (6/12Gbps) serial interface protocol for transporting video streams and configuration data from the Timing-Controller to the OLED display panel.• Developed DisplayPort V1.2 sink IP, supporting four 5.4Gbps main links and a Manchester auxiliary channel.
