Kevin Hwang Email and Phone Number

• WIFI 7(802.11be) – Based on WIFI 6(802.11ax) design, develop algorithms to further improve receiver performance on AGC, packet detection, synchronization as well as mitigation of spur/ACI/DC impairments. Improve radar detection performance under strong ACI scenarios. • RxTD model project lead on all WIFI7 AP projects - Lead and coordinate receiver time domain algorithm and new feature implementation, and support RTL bit/cycle matching. All the code implementation has been done in hybrid MATLAB/system C/C++ platform.• Integrated RF impairment and mitigation models in full sim environment and benchmark end to end performance. • Assisted in chip 11b performance debugging of both WIFI AP and STA chip set.

Join Imagination Technologies through company acquisition• Low power version of WIFI (802.11n/ac) - PHY enhancements and area optimization of AGC, synchronization, carrier offset estimation, RF impairment modeling, RF calibration, FPGA/ASIC validation, system (PHY) level lab testing, and customer on-site support.• Design algorithms to calibrate/compensate RF impairments in MATLAB including estimation and correction of TX LO leakage, TX I/Q imbalance, RX I/Q imbalance, and digital pre-distortion (DPD). Convert algorithms to Python and fixed-point C for lab/field testing and performance improvement using FPGA/ASIC platform.

802.11n/ac physical layer algorithm design

Lead and coordinate a team in the development of China cable (DVB-C) and terrestrial TV (DMBT-H) demodulator designs including algorithm development, fixed point optimization, RTL implementation, as well as FPGA prototyping and testing. The FPGA prototype have passed MII performance requirements.

Led and coordinated a development team for the China terrestrial TV (GB) demodulator design which also included algorithm development, fixed point optimization and FPGA prototypingThe final chips LGS-8G5X and LGS-8G7X series are the major revenue sources of the company Led algorithm team in numerous projects to include algorithm improvement of next generation China terrestrial TV demodulator, and developed and integrated DVB-C algorithms in next generation TV demodulatorsDesigned advanced baseband algorithm for mobile ATSC chip using Matlab

Built and led team of fourteen (14) engineers in ATSC/QAM demodulator IP development which included algorithm design, FPGA prototyping and ASIC optimizationCo-designer for all main modules of baseband demodulators in Matlab and 'C' codePerformed cross verification and debugging with RTL engineersParticipated with lab projects and field tests for demodulator chipsAttended CRC lab for ATSC test - achieves TOV of 14.2dB and passed 44/50 A74 test vectors (both are new records in CRC test history)Coordinated with analog team to define tuner and analog interfaces

Acquired by MediaTek in Sept 2005; also; Led a team in the design of 802.15.4 baseband algorithms and MAC implementationCoordinated in defining RF, Baseband and MAC architectureDesigned baseband algorithm in Matlab; fixed point optimization and generation test plan/test vectorTeamed up with ASIC engineer in RTL/FPGA verification and debuggingCoordinated with RF design engineer on chip level integration and defined test planCompleted ZigBee chip verification, debugging and demonstration

Coordinated and led staff in the system design and algorithm development of WLAN baseband and MAC integrated ASICSpearheaded a team in the design of physical layer baseband algorithmsCoordinated in defining Baseband and MAC architectureParticipated in the design of algorithm in Matlab, fixed point optimization, test plan creation and RTL test vector generationLed ASIC engineer in RTL level verification and debuggingArranged ASIC chip verification/debugging

Defined system specifications and requirements of CALY's proprietary modem chipAssisted with floating-point modeling and fixed point optimization of physical layer baseband algorithm in SPWJointly defined system specifications with MAC and Network layer engineersLed a team in the functional and performance verification in SPW-VERILOG co-simulation environment

Participated in the system design and algorithm development of digital TV baseband chip (ATSC terrestrial TV standard - 8VSB)Participated in Low Earth Orbit(LEO) Iridium satellite communication handset baseband ASIC chip design project Defined receiver structures and interfaces from air interface specificationDesigned floating-point algorithms and fixed-point optimization for all functional blocks in SPWCompleted system performance analysis and hardware complexity tradeoffs among various kinds of synchronization algorithmsReceived "Star Performer" award for big success of the project