Kevin Stevens Email & Phone Number

Toronto, On, Ca

Toronto, Ontario, Canada

Toronto, Ontario, Canada

Manager of oneAPI FPGA and HLS product, compiler, static compiler reports, consisting of 4 teams of 6-8 people + 3 architects totaling 30 individuals at peak. Managed through large attrition of ~20% due to the AI startup boom in Toronto, rebuilding the team to full effectiveness in <1 year, developing new practices for coding, reviewing and documenting to retain knowledge and effectiveness through times of high attrition.Team successfully delivered the FPGA compiler for the initial Intel oneAPI product release in 2020 followed by 3-4 releases per year, consistently delivering the FPGA component on time and meeting performance goals. In late 2023, the team added the SYCL HLS flow to the Intel oneAPI product to better serve a wider range of FPGA customers. During this time the team also added key support for the embedded and industrial markets, including support for latency controls and targeting performance optimizations for vision & video applications.Worked closely with Marketing, Product Planning & Support to define roadmap and prioritize features for the oneAPI product that would best serve FPGA customers’ goals for each release version & the 3-year roadmap. Discussed plans, challenges and improvements directly with customers from a wide range of markets, including FPGA-as-a-service, video streaming, packet processing and complex math operations and robotics.

Toronto, Canada Area

Manager of FPGA OpenCL runtime and static compiler reports, consisting of 3 teams + 1 architects totaling 20 individuals at peak. Oversaw new support and usability features added by team, including HBM support, visual representation of generated system, incremental flows and integrating runtime profile information into VTune. Helped develop and achieve promotion of senior employee to Principal Engineer meeting Intel robust standards to gain this promotion.Personally led the OpenCL toolchain integration plans & discussion between FPGA & CPU/GPU after Intel acquired Altera.

Greater Toronto And Hamilton Area, Ontario, Canada

Manager of FPGA OpenCL runtime and static compiler reports. Grew team from 2 individuals to 10 individuals in less than 1 year, developing several junior members into leadership positions to achieve product goals.Personally acted as OpenCL Engineering Product Lead, responsible for working with Marketing, Product Planning & Product Support organizations to define the roadmap and commitments for each release.

Toronto, Ontario, Canada

Implemented SVM and ICD & ACD/FCD in C in OpenCL runtime (C language), meeting performance goals. Implemented functional image manipulation APIs on FPGA according to OpenCL spec, consisting of OpenCL runtime (C language) & compiler (C++) work.

Toronto, Ontario, Canada

Led team of 10 defining & modeling FPGA core routing fabric through successful, on-time tape outs of 12 Altera FPGA device families. Developed one employee into a management position, which they still held in Q1’24. In 2012 during a difficult transition period, team was recognized as “the perfect role model of teamwork” due to how team worked with internal partners.

Toronto, Ontario, Canada

Wrote C & Perl code to optimize and model portions of wire/mux patterns in the FPGA core fabric, leading to successful tape out of 3 FPGA families meeting all performance goals.