Kevin Glass Email & Phone Number

Scottsdale, Az, Us

Us

Architecture and mm-wave circuit design of data converters, frequency synthesizers, advanced RF communication and fiber optic communication I.C.s.; utilizing IBM 65nm CMOS-10RFE, 45nm CMOS-12SOI, 32nm CMOS-32SOI, and 130nm BiCMOS/SiGe 8HP.100GB and 40GB fiber optics - Coherent Receiver. 1. Design of 66Gsps 6 b flash A/D converter in 8HP, using many new architecture and mm-wave circuit innovations. 2. Highly interleaved 8 bit A/D integrated with DSP, in 32nm CMOS-SOI, for one-chip fiber optic Coherent Receiver. 3. Highly interleaved 6 bit A/D integrated with DSP, in 45nm CMOS-SOI, for one-chip fiber optic Coherent Receiver. 4. Developed 66Gsps 6 b pipelined A/D, requiring innovative new mm-wave circuits and pipeline architecture. 5. 4x22GB, 2x42GB and 44GB fiber optic SERDESs. Systems and circuit support. 6. Four patents issued for new technologies at these frequencies .Band-pass delta-sigma A/D converter – 44Gsps, 200MHz bandwidth, 11 1/2 bits. 1. Development of architecture using MATLAB. Two patents issued on this architecture. 2. Design of a 44 GHz 4 bit flash A/D quantizer, 44 GHz resonators, 44GHz DAC. Massively Parallel Array Delta-Sigma A/D converter. 1. Design of asynchronous delta-sigma modulator and all linear circuits in 0.65nm RF CMOS 10LPE. 2. Micro-architecture, logic and top level chip planning. Point to Point Radio – High data rate network backhaul – 256 QAM at 12/24GHz.

Us

Santa Clara, California, Us

Radio systems architecture for CMOS, BiCMOS/SiGe UMTS multimode cellular phone chipset. Developed link budget system spreadsheet; receiver line-up, including, gain, bandwidth, noise figure, and IIP3, for each circuit block, and A/D dynamic range, to meet WCDMA and EDGE 3GPP requirements. Reviewed transmitter architecture options to merge WCDMA with EDGE. Specified and designed key CMOS, BiCMOS/SiGe circuit blocks. Developed a break through architecture for low voltage MEMs RF switches. Fast track patent awarded for this design.Developed Fractional N Frequency Synthesizer architectures to implement agile and software defined radio, and direct modulation for highly variable PA characteristics and power level control. IDFs submitted and 1 patent filed. Fractional N Frequency Synthesizer - Design and Development of advanced Frequency Synthesizer employing delta-sigma modulation for improved close in carrier phase noise, and polar transmit modulation to eliminate transmitter modulator and up conversion mixer. Design supports Edge, GPRS, and GSM. 1 patent issued. Activity included the following:1. Synthesizer Architecture – Developed Verilog and Matlab Analog Behavioral Models. Specified DSP algorithms.2. Designed critical PLL circuits including, VCO, multimode prescaler, delta-sigma modulator/divider/phase accumulator, PFD/Charge Pump/Loop Filter employing newly derived biquad, voltage regulator employing newly developed self-biased folded cascode opamp, and loop calibration. 3. Coordination of synthesizer floor-planning and layout. Development of mixed signal/ logic design methodologies.4. Demonstrated first silicon functionality of synthesizer design. Passed FTA qualification.Member of WCCG strategic capabilities group, and DTTC technical reviewer. Panelist for 2003 GaAs IC symposium

Santa Clara, California, Us

LXT43001 – Most advanced, highest performance 42G bit OC-768 Limiting Amplifier available when entered production. Designed in InP HBT technology the amplifier exhibits > 40dB gain, > 43GHz bandwidth, 5ps group delay, and < 5ps p-p jitter. The development of this amplifier solved the following key problems: Amplifier architecture that achieved maximum bandwidth with minimum jitter; Bias circuit that gm tracks over PVT; A millimeter-wave minimum parasitic layout with high S12; Input offset cancellation circuit with large dynamic range; Linear and temperature stable input slice adjust circuit; Input and output circuits using Coplanar Waveguides and matching networks for S11 and S22 of –15dB to 40GHz including package and interconnect; Loss of signal peak detect circuit operates at 80GHz down to 10mV.Presented a paper on this chip with measured lab results at ICCD 10/2003 – “Fully Differential Receiver Chipset for 40 Gb/s Applications using InP/InGaAs Single Heterojunction Bipolar Transistors (invited)”. 3 patents issued.Contributed to design of 40Gbit InP HBT distributed amplifier laser modulator driver. 1 patent issued on this circuit.40G bit Limiting Amplifiers in 0.13u CMOS. Two new amplifier architectures were developed that exhibited in lab resultsof 40dB gain, 40Ghz bandwidth, 6ps p-p jitter, 6ps rise/fall times, with good eye diagrams.40G bit Limiting Amplifiers in 80nm CMOS technology. Taped out 3 amplifier designs – one incorporating an innovative offset cancellation circuit outside the RF path. Showed 42dB gain, 55GHz bandwidth and jitter of 2ps p-p. IDF submitted. Key member of team specifying Intel’s 90nm SiGe BiCMOS process. Developed 40G test vehicles and structures.

Santa Clara, California, Us

10Gbit Ethernet, 5Km and 40Km, MSA module design. Developed Optical Link Budgets for IEEE 802.3ae. Designed transponder electronics: TIA, limiting amp, SerDes / PLL bandwidth, laser driver and XAUI I/O. Module electrical design - power supply distribution/bypassing, signal interconnect/integrity, coupling/impedance matching, and performance tunable features. Developed 3 sub-module optical assembly, using a new fiber alignment (IDF filed) to improve manufacturability, isolation and reliability. Designed Fabry-Parot and DFB laser sub-modules including microwave interconnect, biasing, and optical isolator. Developed 1310nm/1550nm receiver, investigating PIN-diode/TIA integration. Evaluated technologies, established foundry relationships, coordinated with other Intel groups in Europe and USA.

Santa Clara, California, Us

Micro-Architecture, advanced technology,and circuit development for the third generation iA64 microprocessor (YOSEMITE). Identified and solved major issues to implement a highly parallel multi-gigahertz microprocessor in 90nm CMOS technology. Cluster Manager for REN, RSE, ISD, BRU units on MERCED (1 million transistors) (30 engineers). Coordinated, planned, and technically supported final logic, circuit design and layout. Major contributor to project level ops teams. 1st silicon functionality.MERCED (1st generation iA64/Itanium processor) STK Unit Manager (400K transistors) (10 engineers). Coordinated, planned and technically contributed to the uarchitecture development, HDL/logic design, circuit design and layout of one of the most timing critical and logically complex units on MERCED. 5 IDFs were filed for circuits, logic, and uarchitecture associated with this unit. Organized and ran circuit and layout reviews for the SE cluster (70% of chip, core execution and floating point), providing design solutions to improve speed and robustness. Key member of Circuit Management Review Committee, Physical MRC, and timing task force. Made major contributions to defining and implementing MERCEDs circuit design methodology. Developed critical circuits for SRAMs (current sensing), Register Files, CAMs, Data Path (Domino, DCVSL, pass gate) and full chip global interconnect (signal requirements, repeaters, clock and power supply distribution).

Santa Clara, California, Us

Spread Spectrum Radio Project – Developed digital radio system architecture, along with low power circuits for radio sub-systems as follows: low noise amplifier, PLL and DDS frequency synthesizer, high speed flash A/D (3 patents issued).PLL Division Expert – Designed spread spectrum PLL used in all HP ink jet printers; 1st silicon went to production. Reviewed all PLL and memory designs division wide. Worked with i960 group to develop a new low power i960 uarchitecture (p200).Digital Imaging – Designed 4 new CMOS active pixel arrays, using new cells that had logarithmic light responses to eliminate shutters for digital camera applications. Designed readout circuitry including column & multiplexed A/D converters. First silicon success. .

RSP; a low power, High MIPs/Watt super scalar DSP for wireless, cellular, and smart phone applications (6M transistors).Developed chip level techniques resulting in exceptionally low power. Architected low power instruction and data caches, performance optimized for DSP and graphics (patent filed). Cache circuits designed: 4M SRAM using current sensing (patented), set tag compare & MUX, FILO victim CAM; 1st silicon success. Analyzed algorithms and developed uarchitecture for the vector unit. Design of arithmetic data paths, including a carry sense ALU (IDF filed), and 6 port register file. Design of low power analog/RF circuits: e.g. a low jitter, fast locking, clock multiplying DLL (patented); 1st silicon success.Cellular (IS-54) communications systems analysis and chip uarchitecture. Identification of technology critical block specs.Developed in cooperation with Berkeley Design Consulting the industry standard for DSP benchmarks.

Msee, Electical Engineering

Course Work And Research Towards Phd In Electrical Engineering

Bsee, Electical Engineering