Khaled Heloue, Ph.D. Email and Phone Number

CAD/Methodology: signoff guidelines, timing margining and statistical modeling, machine learning

Methodology/CAD: Technical lead supporting next generation discrete GPU, APU, and semi-custom SOCs with physical design and signoff guidelines (timing and SI methodology topics, PVT corners, latest margining methodologies, etc...). Expert in variation aware timing analysis

Worked on novel techniques that enable fast and accurate analysis of circuit timing and leakage under process and environmental variability.Advisor: Prof. Farid N. Najm• Early approach to Statistical Static Timing Analysis (SSTA) based on generic paths• First-order SSTA under unknown/incomplete correlations• Linear-time multi-corner static timing analysis• Early- and late- mode full-chip leakage analysis under variability• Parameterized Static Timing Analysis (PSTA)… Show more Worked on novel techniques that enable fast and accurate analysis of circuit timing and leakage under process and environmental variability.Advisor: Prof. Farid N. Najm• Early approach to Statistical Static Timing Analysis (SSTA) based on generic paths• First-order SSTA under unknown/incomplete correlations• Linear-time multi-corner static timing analysis• Early- and late- mode full-chip leakage analysis under variability• Parameterized Static Timing Analysis (PSTA) with nonlinear delay models and uncertain/arbitrary variations• Robustness analysis and metrics in PSTA Show less

Interned at Strategic CAD Labs (SCL) and worked on issues related to timing analysis under variability, robustness analysis, and silicon-to-model improvement.Mentor: Dr. Chandramouli V. Kashyap• Implemented different approaches to parameterized static timing analysis (PSTA) and tested them on various microprocessor blocks• Developed and implemented a novel robustness metric to quantify slacks’ susceptibility to timing failures due to PVT variations• Developed and implemented… Show more Interned at Strategic CAD Labs (SCL) and worked on issues related to timing analysis under variability, robustness analysis, and silicon-to-model improvement.Mentor: Dr. Chandramouli V. Kashyap• Implemented different approaches to parameterized static timing analysis (PSTA) and tested them on various microprocessor blocks• Developed and implemented a novel robustness metric to quantify slacks’ susceptibility to timing failures due to PVT variations• Developed and implemented a silicon-learning framework that uses silicon measurements to improve the ranking of slacks from the pre-silicon step Show less