Architecture and RTL design of VLIW based packet network processorsArchitecture and RTL design of ARM based System-On-Chip SubsystemMicro-architecture and RTL implementation of high performance low latency AXI interconnect fabric and associated multi-port memory controller.Extensive IP integration experiences including DDR memory controllers/PHY, USB, PCIe, I2C, SPI, GPIO, Interrupt Controllers, UARTSpecified subsystem multi-clock domain strategy and CDC analysis. Directed physical team on floor-plan and port placements for high speed synthesis. Designed and implemented AXI Interconnect Fabric. Provide guidance to verification team. Architected and designed Bi-Directional Forwarding capable Packet DMA Engine. Architected on-chip logic analyzer with compression capability.Synthesis and timing closure of ASIC blocksMentoring of junior ASIC design and verification engineers

Verified RAMBUS based memory systems with Specman based testbench. Performed code coverage analysis. Designed and developed network topology stimulus generators for chip level simulation environments.

A key contributor for the design and implementation of a large-scale C-based MP post-silicon verification tool based on the IA-64 architecture. Developed instruction generation, simulation, checking, trap handling, context switch, virtual memory management modules for a complex pseudo-random code generator in an object-oriented C software architecture and the IA-64 assembly language. Brought new team members up to speed and mentored new hires.

Responsible for the electrical characterization, margin testing and frequency design margin tuning of system bus for HP servers.