Kip Stevenson, Phd Email & Phone Number

Portland, Oregon Area

1. As Senior Engineer at Intel, I led Research and Development for novel wafer test probe technology focused on increasing Intel's test competitive advantage and generation of new Intel IP. 2. Took charge of material selections for manufacturing next-generation knowledges (solder pastes, underfills, UV-curables, encapsulants, wet-etch chemistries) and product architecture evaluations for technology proof of concept and manufacturing flow definition. 3. Test Cost Optimization for LCIA Platforms and Products: Completed detailed analysis and experiments with division stakeholders to address test cost reduction opportunities for low-cost IA products. Designed detailed experiments to demonstrate Sort to Class test content and yield matching capability for SLT/DMV to influence alignment of High Density Modular Tester initiative to Cedar View and other LCIA products; achieving a 10x reduction in test cost and enabling consideration of potential content optimization scenarios for Singulated-Die-Test platforms.5. Test Metrology Pathfinding and Development: Initiated several projects to identify novel solutions to address gaps in test equipment health metrologies and test PCS. Successfully worked with test handler supplier to implement IR sensor to detect Interface fluid dispense in CTH test module for 1270 IVB ramp. Completed successful technical analysis and experiments to identify technical challenges and cost reduction opportunities for integration of inertial sensors on Si or Package. _____________________________________________________________________________________________________Professional Experience• 6 Patent Filings and Trade Secrets. • 18+ Peer Reviewed Publications• Adjunct Assistant Professor in Chemistry Department at University of Portland. ____________________________________________________________________________________________________

Portland, Oregon Area

Learn more about my business at www.craftqa.com. • My Craft QA company is a business focused on quality assurance services for Craft beverage industries, providing comprehensive consulting services on Good Manufacturing Practices, Process Technology Control and Monitoring, Custom Beverage Equipment Development, Customer Laboratory Set-up and Training, and 3rd party Laboratory Testing Services (ASBC) and Education. • Evaluated agronomic and commercial viability of new malt barley varieties for locally-sourced supply of specialty malt barley for craft brewing and distilling. • Established a fully OLCC licensed semi-automated Nano brewing system (1bbl) for craft brewing, all grain brewing education, technical quality assurance training and for use in custom recipe and evaluation of specialty malt barley products.• Advanced a manual and semi-automatic beverage canning machine for 32oz sized cans (Crowlers) for direct to customer tap sales at brew-pubs and tasting rooms. • Created a pneumatic micro-malting system for developing customized malt barley for local source supply chains.

• As Senior Engineer at Intel, I led Research and Development for novel wafer test probe technology focused on significantly increasing Intel's test competitive advantage and generation of new Intel IP. • Took charge of material selections for manufacturing of next-generation solder pastes, underfills, UV-curables, encapsulants, wet-etch chemistries & product architecture evaluations for technology proof of concept & manufacturing flow definition. • Test Cost Optimization for LCIA Platforms and Products: Completed detailed analysis & experiments with all stakeholders to address test cost reduction opportunities for low-cost IA products. Designed experiments to demonstrate Sort to Class test content and yield matching capability for SLT/DMV to influence alignment of High Density Modular Tester initiative to Cedar View and other LCIA products; achieving a 10x reduction in test cost and enabling consideration of potential content optimization scenarios for Singulated-Die-Test platforms.• Test Metrology Pathfinding and Development: Initiated several projects to identify novel solutions to address gaps in test equipment health metrologies and test PCS. Drove characterization of various sensors to detect equipment and product and package failure modes. Worked with test handler supplier to implement IR sensor to detect Interface fluid dispense in CTH test module for 1270 IVB ramp. Completed successful technical analysis and experiments to identify technical challenges and cost reduction opportunities for integration of inertial sensors (accelerometers, gyroscopes, magnetometers) on Si or Package.• Drove alignment of 1270 and 1272 thermal diode requirements for test DTS trimming on products with LTD management and Device groups. Drove alignment of TDAU metrology for accurate thermal diode testing for Test Platforms (Sort, BI, Class, PPV) & SRAM test. Completed certification of thermal diode process variation requirements for IVB and HSW products.

• As Senior Test Pathfinding Engineer and Integrator I worked with cross organizational technology development stakeholders, product divisions, and strategic planning groups to define technology risks, Si package assembly-test requirements, design integrated experiments and determination of final test architecture solutions for Intel Package-Test and product road maps for P1268 and P1269 process technologies for low cost mobile products. • Served as Program Manager for 1264 Wafer Test Pathfinding, Test Probe Card Supplier Selections and Process technology qualifications, TD start up and ramp, and process transfer to AFO consolidated wafer test and Fab24 Factories. • Developed first Hot Sort test module capability for wafer level hot testing of CPU for potential defect reduction on 1264 products. • Cross-organizational team leader responsible for integration of an alternative Pb-free packaging interconnect metallurgy and back-end process technologies (Cu + low K ILD w/ SAC) for Intel die-package technology roadmaps and products for 0.13um to 65nm. • As Wafer Testing Integration Program Leader, I drove development, process qualification, and factory ramp and transfer of wafer level testing technologies for 200mm and 300mm Wafer Test.• Project leader responsible for qualifying comprehensive factory automation software suite for 300mm Wafer Test Factory Automation and Manufacturing Systems Technology for D1C Sort factory startup and 1262 Product Ramps. • Project Leader of Wafer Test hardware supplier selections and Wafer Sort Probing qualifications for P1262/1263/1264.• Owner and Approver of Wafer Test Silicon and HW Design rules for Process 860 to 1264 and managing test tooling design interactions with product divisions and tooling design groups.• I designed and developed prototypes, fixtures and lab-based equipment using 3D CAD (Solidworks, Fusion360) and 3D Printing (Stratasys).

Doctor Of Philosophy (Ph.D.), Physical Chemistry

Postdoctoral Fellow, Chemical Structure And Dynamics

Master'S Degree Of Science, Chemistry And Bioengineering

Bachelor Of Science (B.S.) With Honors, Chemistry