Kiran G.

Kiran G. Email and Phone Number

Director and Distinguished AI Research Engineer @ Micron Technology
California, United States
Kiran G.'s Location
Santa Clara, California, United States, United States
About Kiran G.

Dr. Gunnam is an innovative technology leader with vision and passion who effectively connects with individuals and groups. Dr. Gunnam's breakthrough contributions are in the areas of advanced error correction systems, storage-class memory systems, and computer vision-based localization & navigation systems. He has helped drive organizations to become industry leaders through ground-breaking technologies. Dr. Gunnam has 86 issued US patents and 100+ patent applications/invention disclosures on algorithms, architectures, and real-time low-cost implementations for computing, storage, and computer vision systems. He is the lead inventor/sole inventor for 90% of them. Dr. Gunnam’s patented work has been already incorporated in more than 3 billion data storage, WiFi and 5G chips as of 2020 and is set to continue to be incorporated in more than 500 million chips per year.Dr. Gunnam is also a key contributor to the precise localization and navigation technology commercialized for autonomous aerial refueling and space docking applications. His recent patent-pending inventions on low-complexity simultaneous localization and mapping (SLAM) and 3D convolutional neural network (CNN) for object detection, tracking, and classification are commercialized for LiDAR + camera-based perception for autonomous driving and robotic systems. His more recent inventions on machine learning accelerators have ~2x savings vs the state of the art.Dr. Gunnam received his MSEE and Ph.D. in Computer Engineering from Texas A&M University, College Station. He is world-renowned for the balance between strong analytical ability and pragmatic insight into the implementation of advanced technology. He served as IEEE Distinguished Speaker and Plenary Speaker for 25+ events and international conferences and more than 3000 attendees in the USA, Canada, and Asia benefited from his lecture talks.Leadership skills: Hands-on leadership, team building, mentoring, patience, empathy, problem solving, dependability, effective communication, planning, scheduling, organizing, consensus building across large organizations and across industry. Technical Skills: Co-optimization of algorithms, software and hardware, hardware friendly algorithms, hardware architectures, Domain-specific accelerator architectures, VLSI signal processing architectures, computer arithmetic, machine learning, and AI, Computer Vision, advanced ECC, Programming (MATLAB, Python, C/C++, Verilog), EDA tools (ModelSim, NC Sim, VC Sim, Synopsys DC and familiarity with P&R tools).

Kiran G.'s Current Company Details
Micron Technology

Micron Technology

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Director and Distinguished AI Research Engineer
California, United States
Kiran G. Work Experience Details
  • Micron Technology
    Director And Distinguished Ai Research Engineer
    Micron Technology
    California, United States
  • Western Digital
    Distinguished Engineer - Machine Learning & Computer Vision
    Western Digital 2018 - Present
    San Jose, Ca, Us
    Senior Technologist / Distinguished Engineer - Machine Learning & Computer VisionTechnical leadership in algorithms, architectures, and hands-on development for machine learning and computer vision systems for data & video analytics and autonomous systems. Invented and led the prototyping of new domain-specific accelerator architectures for machine learning and computer vision with the co-optimization of algorithms, software, and hardware with the novel ways of fully exploiting sparsity and redundancy to provide ~2x savings vs SOTA. US Patent applications: 20210303976, 20210303909 and 20210191733Provide technical diligence for Western Digital Capital (Investment division of Western Digital).Provide technical diligence for Corporate Development and Strategy at Western Digital Corporation (M&A division of Western Digital).
  • Acm, Association For Computing Machinery
    Acm Distinguished Speaker
    Acm, Association For Computing Machinery Apr 2022 - Present
    New York, Ny, Us
    I am recently appointed as Distinguished Speaker of the ACM for the term of three years from April 2022 to April 2025. ACM’s Distinguished Speaker Program (DSP) is a highly visible way that ACM, through the appointment of leading researchers, engages with emerging professionals, students and, in some cases, the public on a range of topics in computing. I am excited to join this illustrious group to volunteer my time to this important program for the computing community.
  • Valleyml
    Chair (Volunteer)
    Valleyml Jan 2019 - Present
    ValleyML is a cross-industry community for advancing AI to empower people. Served as a Program Chair for State of AI and ML events in 2019 and 2020. Served as a general chair for AI Expo 2020 and 2021. ValleyML has a global outreach to close to 200,000 professionals in AI and Machine Learning. Current and previous sponsors include Edge Impulse, Habana Labs, Efinix, Lattice Semiconductor, MINDBODY, Inc., Think Silicon, Dell, KISSPlatform, Graphcore, UL, Ambient Scientific, SEMI, Intel, Western Digital, Texas Instruments, Google, Facebook, Cadence, and Xilinx.Please see https://valleyml.ai/--Lead instructor for IEEE/ACM/ValleyML Machine Learning and Deep Learning Boot Camp in 2019 and 2020.Please see https://valleyml.thinkific.com/bundles/machine-learning-and-deep-learning-boot-camp for the information on the boot camp. These boot camps originally evolved from the following:1. Graduate course Dr. Gunnam designed and taught at Santa Clara University as an adjunct professor 2. IEEE Machine Learning and Deep Learning Workshop designed and taught by Dr. Gunnam in 2017 and 2018.Now these boot camps are further evolving to a fellowship program led by multiple instructors from several companies including Google, Nvidia etc. Please see https://valleyml.ai/fellowship/
  • Ieee
    Industry Member On Ieee Cass Board Of Governors
    Ieee Jan 2021 - Present
    Piscataway, Nj, Us
    Volunteering role to promote industry participation and contribution in IEEE Circuits and Systems Society Conferences to attract industry research. Leading a new initiative on Standards activities. Please see https://ieee-cas.org/standards-activitiesAlso the working group chair for IEEE Standard for Arithmetic Formats for Machine Learning. Please see bit.ly/ieee_ml_fp for more info on this working group P3109. Direct link for PAR: https://drive.google.com/file/d/1pZpdk3jaX9Djd9hTmjuRVAe21DEaqZll/view
  • Velodyne Lidar, Inc.
    Technical Director Of Algorithms
    Velodyne Lidar, Inc. 2016 - 2018
    Drove innovation in LiDAR based computer vision for self-driving cars. As a hands-on technical director, I was involved in inventing new ideas, filing invention disclosures for patents, quick prototyping/demos and production software. Innovating on state of the art technologies in LiDAR signal processing, Perception and other higher layers of self-driving stack including object detection and tracking using machine learning, simultaneous localization and mapping, HD-map generation.• Technical contributions : 1) Developed sensor detection, processing algorithms, hardware architectures to improve the range and accuracy of the sensors and robustness to cross talk. Helped the company to deliver VLP-32C and VLP-16 sensors in volume. This resulted in 4x revenue to $175 Million in 2017 compared to 2016. 2) Developed a new reduced complexity LiDAR SLAM 3) Preliminary PoC on 3D object detection, tracking and classification using machine learning. Object classification using combination of SVM, 2-D CNN and 3-D CNNs. Individual work in progress: LiDAR+camera to identify key features and using both to build robust semantic features from multiple trips for localization.• Built a diverse team of 10 and led 1) RoS drivers for sensors 2) LiDAR+ camera integration 3) LiDAR+IMU integration 4) Sensor Processing algorithms and modeling including new analog ASICs. 5) Sensor auto-calibration PoC. • 9 patent applications with lead inventor for 5 of them. Presentations on work [1] “Low Complexity Real-Time Simultaneous Localization and Mapping Using Velodyne LiDAR Sensor”, GPU-Tech, 2018 Similar talks at IEEE Robotics. [2]. IEEE Workshops on Machine Learning and Convolutional Neural Networks, May 2017**Team work in 2018 at Alameda: Evaluated simplistic heuristics based grid and line based approaches for 3d modeling and proved that these do not work as compared to rigorous methods based on fused features using camera + LiDAR + IMU in multiple trips.
  • Western Digital
    Technologist
    Western Digital 2014 - 2016
    San Jose, Ca, Us
    Worked as part of research group in CTO team on conceiving, prototyping and guiding development of new storage and computing related projects and ideas, as well as writing invention disclosures and research publications. Primarily working on storage class memory (SCM) based storage systems and in-situ processing (executing code within the storage device). Lead the prototyped ideas to commercial products.Provide technical diligence for Western Digital Capital (Investment division of Western Digital).Provide technical diligence for Corporate Development and Strategy at Western Digital Corporation (M&A division of Western Digital).***Significant work includes the invention and prototyping of ultra-low latency wear leveling system for storage class memory systems. Matlab modeling of overall system (hardware+firmware) along with RTL coding of the hardware access network. Collaborated with several research group members and the design teams to improve the overall solution.Also worked on developing a very low-latency error correction system for storage class memory systems. Matlab modeling of the system along with providing the hardware architecture document to the design team. Collaborated with research group in Israel to further improve the solution.More than 20 invention disclosures and 15+ patent applications.
  • Ieee
    Ieee Distinguished Speaker
    Ieee 2013 - 2015
    Piscataway, Nj, Us
    As an IEEE SSCS Distinguished Speaker, Dr. Gunnam has been invited to give 19IEEE Distinguished Lectures in the US and overseas on VLSI architectures for signalprocessing and implementation, with a focus on his contributions to LDPC. More than2000 attendees in USA, Canada and Asia benefited from these talks. The hosts includeSSCS chapters as well as companies like Samsung Korea and SK Hynix Korea.IEEE Distinguished Lectures: IEEE SSCS Orange County: June 29th 2013; IEEE SSCSDenver: July 22nd 2013; IEEE SSCS in Dallas: August 19th 2013; IEEE Central NorthCarolina Section, August 20th 2013; IEEE SSCS in Toronto, Ottawa, Montreal: Sept3rd/5th/6th; IEEE SSCS in New Delhi: Dec 19th 2013; Plenary Talk at IEEE CONECCT,IISc Bangalore Jan 7th 2014; IEEE SSCS Singapore Jan 9th 2014, UC San DiegoApril 17th 2014, UT Austin April 21st 2014. IEEE SSCS Lehigh Valley and PrincetonChapter May 1st 2014, Columbia University May 2nd 2014. East Asia [Tokyo, Kyoto,Seoul, Samsung, SK Hynix : November 2014]Report of my DL talks:http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6670194Report on Bangalore Visithttp://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6841703Report on Singapore Visithttp://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6841790From http://www.ieee.org/about/volunteers/tab/distinguished_lecturer_program.htmlIEEE Distinguished Lecturers are engineering professionals who help lead their fields in new technical developments that shape the global community. These experts:specialize in the field of interest of their Society/Council;travel to various technical and regional groups, such as Society and Technical Council Chapters, to lecture at events.
  • Violin Memory
    Director Of Engineering
    Violin Memory 2013 - 2014
    Colorado Springs, Colorado, Us
    Signal Processing and Advanced Error Correction Coding systems, Data processing algorithms, Queuing systems, System Hardware architecture and implementation. Array processing.
  • Nvidia
    Lead Architect/Micro-Architect
    Nvidia 2011 - 2013
    Sr. Hardware Engineer. Member of Tegra memory controller ASIC group that worked on high-bandwidth multi-client memory subsystems (clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth). A great learning experience in understanding memory system architectures from DRAM up. My contributions to Tegra are busrouter model infrastructure, programming and validation of multi-phase clock distribution buffer, help in several verification and bringup issues. Collaborated with security hardware group and defined micro-architecture definition for a new security feature.
  • Certicom
    Lead Architect/Micro-Architect
    Certicom 2011 - 2011
    Mississauga, Ontario, Ca
    Sr. ASIC Design Engineer. Research and development of Security ASIC IP that goes as part of application processors. Filed patent applications on cryptography implementation with countermeasures. Worked on the development of security ASIC IP and RTL design.Issued patents------------------ 8,334,705 Analog circuitry to conceal activity of logic circuitry 8,627,131 Hardware countermeasure against cryptographic attack 8,635,467 Integrated circuit with logic circuitry and multiple concealing circuits
  • Lsi, An Avago Technologies Company
    Principal Read Channel Architect
    Lsi, An Avago Technologies Company 2008 - 2011
    San Jose, Ca, Us
    Joined as Principal ASIC Development Design Engineer (Senior Manager Grade) with in a year after PhD. It takes usually 4 to 8 years to become a Principal engineer in LSI after PhD.Advanced Error Correction Coding systems. LDPC based iterative systems with statistical buffering (queuing). Lead architect for several key blocks LDPC decoder, error floor mitigation, interleaver, turbo equalization system, queuing system and write path. Instrumental in the design of efficient and novel algorithms and hardware system architectures for read channel systems based on my PhD work at Texas A&M. High performance and low silicon area of designs based on Texas A&M LDPC work helped secure several multiple-billion dollar design wins for LSI during the HDD market's transition from Reed-Solomon based read channels to LDPC-only based read channels. The systems I designed are still used in several generations with incremental changes. 32 issued patents. Several recognition awards (including Bravo and Winner’s Circle) at LSI.Some of my LSI patents that reference and use earlier LDPC patent applications at Texas A&M as base work. These are used in high volume LSI Truestore read channels such as McLaren and Spyder and its derivatives------------------------------------------ 8,448,039 Error-floor mitigation of LDPC codes using targeted bit adjustments 8,402,348 Systems and methods for variable data processing using a central queue 8,402,324 Communications system employing local and global interleaving/de-interleaving 8,768,990 Reconfigurable cyclic shifter arrangement --modifies shifter in layered decoder while using the same layered decoder datapath from Texas A&M patent applications. 8,499,226 Multi-mode layered decoding - Uses the same layered decoder datapath from Texas A&M patent applications in both modes (normal and special), special mode decodes the high row weight layer with smaller circulant size along with normal layers
  • Marvell Semiconductor
    Senior Read Channel Architect
    Marvell Semiconductor 2006 - 2008
    Santa Clara, Ca, Us
    Sr. Design Engineer. Advanced Error Correction Coding systems. LDPC based iterative systems. Defined the base architectures for LDPC decoder and interleaver that are now widely used in Marvell's read channel products based on my PhD work. Architect and designer for LDPC decoder. Also provided architecture solutions for encoder.Some of the issued patents:------------------------------------ 8,291,292 Optimizing error floor performance of finite-precision layered decoders of low-density parity-check (LDPC) codes 8,196,010 Generic encoder for low-density parity-check (LDPC) codes 8,065,598 Low latency programmable encoder with outer systematic code and low-density parity-check code 8,044,832 Interleaver for turbo equalization 7,911,364 Interleaver for turbo equalization
  • Texas Engineering Experiment Station / Starvision Technologies
    Research Engineer / Graduate Research Assistant
    Texas Engineering Experiment Station / Starvision Technologies 2004 - 2006
    Computer Vision and signal processing systems for navigation and space SDR (DSP and FPGA).Defense and space projects as well as commercial products.Technology commercialized for autonomous aerial refueling applications through Sargent Fletcher.Sargent Fletcher is a subsidiary company of Cobham plc. which makes aircraft equipment, including aerial refueling systems, external fuel tanks, and special purpose pods.Technology is also licensed to NASA for space craft docking.
  • Schlumberger Technologies
    Dsp Engineer / Co-Op
    Schlumberger Technologies 2004 - 2004
    Modem design (DSP and FPGA).
  • Intel Corporation
    Design Engineer / Co-Op
    Intel Corporation 2002 - 2003
    Santa Clara, California, Us
    Part of Instruction Cache group.
  • Texas Engineering Experiment Station
    Sensor Processing & Navigation Engineer / Graduate Research Assistant
    Texas Engineering Experiment Station 2000 - 2002
    Research and Development of computer vision and signal processing systems for navigation (DSP and FPGA).http://dnc.tamu.edu/projects/smartsensors/visnav.htmlTechnology later commercialized for autonomous aerial refueling applications through a start up Starvision Technologies and Sargent Fletcher.Sargent Fletcher is a subsidiary company of Cobham plc. which makes aircraft equipment, including aerial refueling systems, external fuel tanks, and special purpose pods.Technology licensed to NASA for space craft docking.

Kiran G. Skills

Asic Fpga Digital Signal Processors Embedded Systems Hardware Architecture Rtl Design Semiconductors Algorithms Vlsi Signal Processing Field Programmable Gate Arrays Soc Simulations Verilog Application Specific Integrated Circuits Matlab Integrated Circuit Design Very Large Scale Integration Computer Architecture Logic Design Ic System On A Chip Firmware Microarchitecture Processors Systemverilog Microprocessors System Architecture Debugging Arm Integrated Circuits Ldpc Low Power Design Arm Architecture Software Development Software Project Management Machine Learning Agile Project Management Management Leadership Analog Vhdl Eda Static Timing Analysis Modelsim Theoretical Computer Science Encryption Tcl Computer Vision

Kiran G. Education Details

  • Texas A&M University
    Texas A&M University
    Computer Engineering

Frequently Asked Questions about Kiran G.

What company does Kiran G. work for?

Kiran G. works for Micron Technology

What is Kiran G.'s role at the current company?

Kiran G.'s current role is Director and Distinguished AI Research Engineer.

What is Kiran G.'s email address?

Kiran G.'s email address is ki****@****ail.com

What is Kiran G.'s direct phone number?

Kiran G.'s direct phone number is +140880*****

What schools did Kiran G. attend?

Kiran G. attended Texas A&m University.

What are some of Kiran G.'s interests?

Kiran G. has interest in Technology, Chess, Reading, Tennis, Travel.

What skills is Kiran G. known for?

Kiran G. has skills like Asic, Fpga, Digital Signal Processors, Embedded Systems, Hardware Architecture, Rtl Design, Semiconductors, Algorithms, Vlsi, Signal Processing, Field Programmable Gate Arrays, Soc.

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