Kit Lam Cheong Email & Phone Number

OpenCl 1.1/embedded profile compiler development targeted for GPU.

 Manage the First Encounter R&D team in delivering prototyping and hierarchical design solutions to the design of complex chips, which spans several geographical locations from San Jose to Noida to Shanghai. The team provided infrastructure for the interoperation of the applications within the system, from design import/export, floorplanning, design partitioning, analysis to place and route. Led team in effectively working synergistically with cross functional teams from product engineering, placement and route R&D, and field engineering to develop prototyping flow methodology for the design community. To address large design challenges and predictability of project closure, directed the team to develop the method to partition a design into smaller pieces so that each one can be tackled independently. In the process, team members developed the underlying partitioning technologies in feedthrough insertion, pin assignment, timing budgeting that are dominant in the EDA industry. Interacted with global customers in Europe, Asia and India on a consistent basis ensuring open communication to make key decisions in a timely manner.

 Architect and developer of the static timing analyzer in First Encounter. The timing analysis engine was developed from scratch and accepted all industry standard input formats from .lib, .tlf, SDC, SDF, spef. At the time, the performance was at least several times better than Primetime. The engine supported the Encounter applications such as timing driven placement (AmoebaPlace), IPO, timing budgeting in hierarchical design flow.

 Project lead in the Formalcheck VDHL, Verilog frontend that generated HDLCar structures feeding into the model checking engine.

Led the digital design team on simulation/analysis tools ­ quickhdl, verilog-XL, pathmill, powermill, timemill, railmill, Zycad hardware accelerator, LSIM, design-time... Monitored license usage; installation and regression testing of new software before being released.Partnered with EDA vendors on setting direction for future tool development and enhancement requests and software bug management; established seamless flow among different vendor tools.Closely interacted with the DSP group to verify the functionality of a new DSP design by performing mixed RTL, gate and transistor level co-simulation using quickhdl and Lsim. The successful exploitation of the simulation strategy contributed to the timely tape out of the new design.Surveyed next generation verification technologies in anticipation of future design needs ­ cycle based simulation, formal verification, and hardware/software co-design.Led a team of 20 circuit designers and CAD engineers to evaluate and select a mixed signal simulation tool which could support the whole spectrum of Rockwell's design disciplines, from mixed-signal, full custom to ASIC. Mentor Graphics' ELDO/Quickhdl emerged as the tool of choice and was deployed.Led a team of 5 engineers to evaluate STA tools ­ motive, primetime, showtime, pearl, taco ­ for full chip gate level timing analysis. Evaluation completed in 2 months. Synopsys' Primetime was selected and was incorporated into the ASIC design flow

Project leader of AGMIDAS - a hardware accelerator for logic simulation, with speed up to 20 times of comparable software simulator on Sun Sparc 10. Coordinated the software deployment and development efforts of a team of 4 software developers and the user support of ~50 circuit designers. Demonstrated superiority over competition in accuracy, performance and ease of use; Developed features to improve simulator flexibility and accuracy by exploiting the power of modeling, and co-simulation on both hardware and software simulators;Resolved tool or model related problems so that tight release schedules were met.Key developer of a hybrid (path and block oriented) static timing analyzer TACO.TACO excelled over conventional static timing analyzer in terms of controllabilityand observability. Its high speed response enabled designers to interactively debug different areas of their designs with ease and reliability. It was also used to generate circuit timing parameters and constraints for each optimization run and the final verification for timing violation on the netlist produced from each run.Jointly designed a new architecture for a simulation system MIDAS. The design involved an object oriented database that optimized end to end data flow with dedicated design language compilers that eliminated ambiguity, and application specific data structures that emphasized modularity and efficiency. Developed a common command parser shareable among tools under the same framework.Developed a compiler for a hardware description language FPDL in which cell-level delays and capacitances can be described in linear or non-linear table models. A set of object oriented functions for the storage and retrieval of functional/timing data were constructed that supported a cell-level delay calculator, and among other design verification tools a min/max simulator, hazard analyzer and logic synthesis for both ASIC and board level designers.

Bs, Mathematics And Computer Science

Ms, Computer Science