Kiran Jayanthi

Kiran Jayanthi Email and Phone Number

Solutions Architect @ Cadence Design Systems
Kiran Jayanthi's Location
Austin, Texas Metropolitan Area, United States, United States
Kiran Jayanthi's Contact Details
About Kiran Jayanthi

Specialties: ARM CPU's, Physical Design, Synthesis, STA, High Performance Digital Design, SOC-Encounter, RTL-Compiler, LEC, Celtic , Low Power Methodologies and TCL programming

Kiran Jayanthi's Current Company Details
Cadence Design Systems

Cadence Design Systems

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Solutions Architect
Kiran Jayanthi Work Experience Details
  • Cadence Design Systems
    Solutions Architect
    Cadence Design Systems Jan 2022 - Present
    San Jose, California, Us
    View
  • Ibm
    Io Integration Lead
    Ibm Dec 2018 - May 2021
    Armonk, New York, Ny, Us
    View
  • Cadence Design Systems
    Solutions Architect
    Cadence Design Systems Jan 2015 - Dec 2018
    San Jose, California, Us
    View
  • Atoptech
    Sr. Staff Sales Application Engineer
    Atoptech Jan 2014 - Jan 2015
  • Mediatek
    Senior Member Of Technical Staff
    Mediatek Oct 2012 - Dec 2013
    Hsin-Chu, Tw
    L2 Cache and NONCPU Physical Design Implementation
    View
  • Texas Instruments
    Cpu Physical Design Lead
    Texas Instruments Oct 2011 - Oct 2012
    Dallas, Tx, Us
    OMAP5430
    View
  • Texas Instruments
    High Performance Physical Design
    Texas Instruments Jan 2010 - Oct 2011
    Dallas, Tx, Us
    OMAP 5430:Physical Design for A15 CPUFlow & Methodology development
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  • Cadence
    Core Comp Technical Leader
    Cadence Jul 2001 - 2009
    San Jose, California, Us
    Experience Summary Excellent experience in pre-sales/post-sales/design services with thorough understanding and knowledge of Digital Physical Design Worked as a fire-fighter in the Digital Implementation Area for 6+ years at several companies Trained teams in India, Brazil and North America on multiple Cadence flows and design methodologies Expert in SOC-Encounter, NanoRoute, QRC, Abstract Generator, RTL-Compiler, Conformal LEC, Celtic , Low Power Methodologies and TCL programming
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Kiran Jayanthi Skills

Static Timing Analysis Physical Design Low Power Design Soc Semiconductors Tcl Timing Closure Place And Route Eda Logic Synthesis Asic Integrated Circuit Design Verilog Cadence Conformal Lec Mips Processors Rtl Design Hardware Architecture Timing System On A Chip Integrated Circuits Vlsi Ic Arm Mixed Signal Very Large Scale Integration Application Specific Integrated Circuits Arm Architecture

Kiran Jayanthi Education Details

  • Clemson University
    Clemson University
    Ee
  • Pondicherry University
    Pondicherry University
    Electrical Electronics Engg

Frequently Asked Questions about Kiran Jayanthi

What company does Kiran Jayanthi work for?

Kiran Jayanthi works for Cadence Design Systems

What is Kiran Jayanthi's role at the current company?

Kiran Jayanthi's current role is Solutions Architect.

What is Kiran Jayanthi's email address?

Kiran Jayanthi's email address is kj****@****ail.com

What schools did Kiran Jayanthi attend?

Kiran Jayanthi attended Clemson University, Pondicherry University.

What skills is Kiran Jayanthi known for?

Kiran Jayanthi has skills like Static Timing Analysis, Physical Design, Low Power Design, Soc, Semiconductors, Tcl, Timing Closure, Place And Route, Eda, Logic Synthesis, Asic, Integrated Circuit Design.

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