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Kiran Jayanthi Email & Phone Number

Solutions Architect at Cadence Design Systems
Location: Austin, Texas Metropolitan Area, United States 8 work roles 2 schools
2 work emails found @cadence.com LinkedIn matched
✓ Verified August 2026 4 data sources Profile completeness 100%

Contact Signals · 2 work emails

Work email k****@cadence.com
LinkedIn Profile matched
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Current company
Role
Solutions Architect
Location
Austin, Texas Metropolitan Area, United States

Who is Kiran Jayanthi? Overview

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Quick answer

Kiran Jayanthi is listed as Solutions Architect at Cadence Design Systems, based in Austin, Texas Metropolitan Area, United States. AeroLeads shows a work email signal at cadence.com and a matched LinkedIn profile for Kiran Jayanthi.

Kiran Jayanthi previously worked as IO Integration Lead at Ibm and Sr. Staff Sales Application Engineer at Atoptech. Kiran Jayanthi holds Ms, Ee from Clemson University.

Company email context

Email format at Cadence Design Systems

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{first_initial}{last}@cadence.com
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AeroLeads found 2 current-domain work email signals for Kiran Jayanthi. Compare company email patterns before reaching out.

Profile bio

About Kiran Jayanthi

Specialties: ARM CPU's, Physical Design, Synthesis, STA, High Performance Digital Design, SOC-Encounter, RTL-Compiler, LEC, Celtic , Low Power Methodologies and TCL programming

Listed skills include Static Timing Analysis, Physical Design, Low Power Design, Soc, and 25 others.

Current workplace

Kiran Jayanthi's current company

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Cadence Design Systems
Cadence Design Systems
Solutions Architect
AeroLeads page
8 roles

Kiran Jayanthi work experience

A career timeline built from the work history available for this profile.

Io Integration Lead

Ibm

Armonk, New York, Ny, Us

Dec 2018 - May 2021

Sr. Staff Sales Application Engineer

Atoptech
Jan 2014 - Jan 2015

Senior Member Of Technical Staff

Hsin-Chu, Tw

L2 Cache and NONCPU Physical Design Implementation

Oct 2012 - Dec 2013

Cpu Physical Design Lead

Dallas, Tx, Us

OMAP5430

Oct 2011 - Oct 2012

High Performance Physical Design

Dallas, Tx, Us

OMAP 5430:Physical Design for A15 CPUFlow & Methodology development

Jan 2010 - Oct 2011

Core Comp Technical Leader

San Jose, California, Us

Experience Summary Excellent experience in pre-sales/post-sales/design services with thorough understanding and knowledge of Digital Physical Design Worked as a fire-fighter in the Digital Implementation Area for 6+ years at several companies Trained teams in India, Brazil and North America on multiple Cadence flows and design methodologies Expert in SOC-Encounter, NanoRoute, QRC, Abstract Generator, RTL-Compiler, Conformal LEC, Celtic , Low Power Methodologies and TCL programming

Jul 2001 - 2009
2 education records

Kiran Jayanthi education

Ms, Ee

Clemson University

B Tech, Electrical Electronics Engg

Pondicherry University
FAQ

Frequently asked questions about Kiran Jayanthi

Quick answers generated from the profile data available on this page.

What company does Kiran Jayanthi work for?

Kiran Jayanthi works for Cadence Design Systems.

What is Kiran Jayanthi's role at Cadence Design Systems?

Kiran Jayanthi is listed as Solutions Architect at Cadence Design Systems.

What is Kiran Jayanthi's email address?

AeroLeads has found 2 work email signals at @cadence.com for Kiran Jayanthi at Cadence Design Systems.

Where is Kiran Jayanthi based?

Kiran Jayanthi is based in Austin, Texas Metropolitan Area, United States while working with Cadence Design Systems.

What companies has Kiran Jayanthi worked for?

Kiran Jayanthi has worked for Cadence Design Systems, Ibm, Atoptech, Mediatek, and Texas Instruments.

How can I contact Kiran Jayanthi?

You can use AeroLeads to view verified contact signals for Kiran Jayanthi at Cadence Design Systems, including work email, phone, and LinkedIn data when available.

What schools did Kiran Jayanthi attend?

Kiran Jayanthi holds Ms, Ee from Clemson University.

What skills is Kiran Jayanthi known for?

Kiran Jayanthi is listed with skills including Static Timing Analysis, Physical Design, Low Power Design, Soc, Semiconductors, Tcl, Timing Closure, and Place And Route.

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