Kailash Nathan Email & Phone Number

Davidson, North Carolina, Us

Interface with customers, drive technical solutions, ensure product quality and customer needs are met.

Davidson, North Carolina, Us

Davidson, North Carolina, Us

- Resolve vendor issues and push for critical application fixes before customer release- Perform release gating activities (feature testing, regression, final no / no-go decision), release documentation and deliver- Interface with customers, gather requirements, pitch solutions and verify end to end flow matches customers wants.

Santa Clara, California, Us

• Managed 20 execution systems and technicians ensuring that test failure from previous night were triaged/debugged, enabled and kicked off new tests, ensuring maximum throughput and efficiency in automation.• Maintained a central repository of information on Wiki pages (FW versions, BIOS, Board rework levels)• Filed and followed up on existing issues with other engineers, designers and architects to track progress • Supported requests to test new IVI firmwares and report results.

Santa Clara, California, Us

On short notice helped plan a power-on strategy with cross-site teams.Managed a small technical team in enabling features related this SoC platform.Supported and debugged issues during power-on from board level, to firmware and up to OS level.Documented board re-works, procedures, maintained a central repository of information. Filed, managed open issues in a defect tracking database to track progress and provide learnings for future projects.

Santa Clara, California, Us

Integrated and sanity tested FPGA image drops. Interfaced with model build team, added and enabled custom firmware ensuring IPC communication between Security and Power engines was functional before release to the customer.Enabled Secure Boot functionality and enabled power and reset sequences flows using external PMIC. Developed and maintained a regression test suite to ensure a quality FPGA image release.to customers.Provided priority support for FPGA image issues using custom software, scripts, JTAG debuggers (Lauterbach, ITP/XDP), Oscilloscopes and on-FPGA Xilinx ChipScope.Documented resolution and shared learnings with internal customers, and drove customer's software and hardware issues to resolution.

Santa Clara, California, Us

Performed System level tests running concurrent traffic between cores, cache, and graphics engines on Intel's Haswell client products for desktop, mobile and Ultra-mobile SKUs. Performed debug and triage using internal tools, gathering register dumps and processor state information. Reproduced issues in pre-silicon emulation environments and helped root cause issues with designers and architects. Performed coverage analysis and intent verification to ensure queue depths, table entries and cache coherency conditions were exercised.● Used an internal Linux operating system: Silicon Validation Operating System with custom drivers with hooks into Core registers and MMIO space and memory target drivers to exercise the data paths in the product.● Developed and maintained Perl, Python scripts to stress embedded DRAM controller and internal multi-chip package busses.

Santa Clara, California, Us

Validated the DDR3 memory controller on SandyBridge client products.Performed debug and triage using a variety of internal tools from gathering BIOS serial logs to register and memory dumps. Probed failing vendor/customer DIMM modules using interposers, logic analyzers and oscilloscopes. Debugged OEMs and vendor DIMM problems as well as submitted fixes for internal and third party tools.● Managed twenty execution platforms and ran “Memory Matrix” - running tests over different DDR3 vendors, speeds, timings, processes.● Developed automation scripts to rotate between memory stress tests, reset testing.● Identified DDR3 probe points using raw card schematics / Cadence Allegro software.

Us

Design and develop tools and applications in order to validate and stress MathStar's reconfigurable processors. The applications require strong knowledge of digital design principles and the ability to perform timing analysis on a clock cycle boundary, in order to separate critical timing sections from non-critical timing sections.Working with applications and hardware engineers to understand how the chip may be used and test not only the major usage models, but also exercise silicon paths that the user may not.

Santa Clara, California, Us

Developed and maintained code for NPE Ethernet / Hash / AES / DES / SDC (ATM, HDLC) Coprocessors. (IXP 5xx series)Executed and debugged assembly / C code on emulation and post-silicon platforms.Collaborated closely with FPGA, validation and design engineers to debug RTL issues.Developed and maintained in-house test infrastructure to automate reporting of results.Created and maintained work flow documents: test plans, test feature matrix, schedules.Participated in test plan reviews, code reviews and coverage analysis.

Boston, Massachusetts, Us

Lab management and supervision: Managed multiple labs as a shift worker, up to 3 shifts a week.Provided customer support to users, and taught them to use Mac/PC systems, printers and software (Microsoft and Apple products)

Miami, Florida, Us

Informing and assisting customers on hardware and software solutions in the Mac and PC sales division. Ensuring the customer walked out with a product tailored to their price pointStocking ShelvesInventory LookupCustomer negotiationSales Follow-upsBundling and promotional sales

Bachelor Of Engineering (B.E.), Computer Systems Engineering

Bachelors, Computer Engineering, Computer Science