Will Kohut Email & Phone Number

I'm currently leading the development of ultra-low latency tick-to-trade and pre-trade risk check systems built using FPGA technology.Trading Protocols: FIX/SBE, MDP, OMD, XDP, OPRA, CTS/CQS, iMpactGitHub: github.com/kohutw1/rtl_design_samplesAt cPacket, I led the development of low-latency FPGA hardware for use in analyzing market data feeds for high-frequency trading / HFT, exchange, and banking applications on 10G, 40G, and 100G Ethernet networks. The design was deployed within the NYSE.As an FPGA and ASIC engineer in the chip industry for 12 years, I've been involved with all aspects of the digital design cycle. This includes architecture specification, RTL coding in SystemVerilog, waveform debugging, synthesis, static timing analysis, verification, coverage closure, performance debug, power optimization, timing/functional ECO implementation, and mentorship of junior engineers.I have experience working on small teams at startups and on large teams at established companies.In my startup experience, I was one of five ASIC engineers that developed the first version of a GNSS/GPS receiver baseband accelerator. I participated in nearly all aspects of design and verification from concept to tapeout and worked closely with my teammates to meet an aggressive ten-month chip schedule. I was involved with the design of datapath blocks, interconnection networks, and CDC interfaces.At NVIDIA, I made contributions to 6 architectural generations of GPU ASICs, all of which have shipped in high volume around the world. Highlights of my work there include:1. Significant redesign of GPU compute pipeline to support simultaneous compute and graphics workloads, resulting in industry-leading performance for asynchronous compute DirectX API feature used to accelerate nearly all next-gen graphics applications.2. Implementation of an L0 instruction cache.3. Verification of numerous texture subunits and the texture unit as a whole. This included the verification of a major rework of the texture pipeline to support cache sharing between compute and graphics workloads.

Listed skills include Asic, Vlsi, Architecture, Hardware Architecture, and 16 others.