Kopperla Janesh Paul Email & Phone Number

Bengaluru, Karnataka, India

Bengaluru, Karnataka, India

Have 3 years of experience mostly exposed to physical design work having skill of floorplan, power plan, STA, Timing ECO's in subsystem level, hands on experience in Fusion compiler, ICC2 and Innovus worked in 3nm, 7nm with Intel and TSMC foundries.

Bengaluru, Karnataka, India

Physical Design trained with Three projects namely DTMF, FALCON, JBI. Good experience in RTL to GDSII of ASIC design flow – Synthesis, Sanity Checks, Floor planning, Placement, CTS, Routing, Signoff.Trained on design technology 28nm. Fixing the Pg_drc in the Power Plan. Physical Verification fixing LVS and DRV’s. Congestion analysis after the placement, improving congestions by placing various placement blockages. Floorplan has become major thing for better QOR. Performed Floorplan experiments to achieve a better Floorplan.

Doctor Of Philosophy - Phd, Electrical Engineering, 85.50% ( First Semester)

Activities and Societies: Research work on Power Quality improvement and Non Conventional Energy

Master Of Technology - Mtech, Power Systems, 8.91/10 Cgpa

Bachelor Of Technology - Btech, Electrical And Electronics Engineering, 64%