Silicon architect for the Achronix flagship device SoC. Responsible for architecture and development of all hardened logic in our devices, including PCIe, Ethernet, CPU, and external memory, as well as all specialized FPGA tiles, such as BRAMs, DSPs, machine learning tiles, and the NoC. Architect and visionary of the Achronix 2D Noc hardware and software solutions, Including introducing a differentiated FPGA design paradigm and software flow.Led the development and software modeling of the hardened blocks inside the FPGAfabric, including our NoC tiles and Machine Learning Processor blocks.Led high speed (112 Gbps PAM4) circuit board design and overall silicon bringup activitiesfor our flagship silicon.

My responsibilities include managing the Software & Hardware organizations, including responsibility for high-quality and on-time implementation of all of Arteris' products. our recent focus is highly configurable cache-coherent interconnect IP.My responsibilities have included:* Growing the HW and SW teams.* Establishing test and quality reporting metrics and mechanisms* Writing the microArchitecture documents for the cache coherent units.* Managing the development of the Javascript customer-facing interconncet design application.* Personally implementing the cache coherency manager and snoop filters.

Leads a large engineering staff, with 5 teams across 3 continents.Responsible for the System Design, IP Infrastructure, Debug & Instrumentation, and Quartus Programmer portions of Altera’s SW portfolio, as well as the test platform for new device checkout.Has grown a strong multi-site engineering & management team, growing and mentoring engineers and managers.Has grown the Qsys system design tool to where it’s used in a significant portion of Altera designs, and supports Altera’s SoC platform, OpenCL, and Video IP Suite.Successfully led several significant cross-functional projects, including: o First-time success of Altera’s SoC FPGA compilation support, Altera's most complex IP core to date, with members from atom modelling, synthesis, place-and-route, timing modeling, power modelling, & embedded software teams. o A multi-year project to standardize IP Development in Altera. o Altera's internal UVM BFM task force, responsible for developing UVM-based verification IP for Customer IP and internal IC Design teams.Consistently drives Quality improvement efforts.Helped win DesignCon 2014's "Outstanding FPGA and SoC Innovations" award for SOC & FPGA cross-triggering & adaptive debugging.

Architected and implemented the proof-of-concept Qsys NOC interconnect, as Master’sthesis. Subsequently led the team to develop and productize it as “Qsys” in a fraction ofthe time taken to develop SOPC Builder, the tool that Qsys replaced.Initiated and grew the Hw.tcl IP platform to where it supports all of Altera’s IP, andprovides ease-of-use and capabilities beyond that of the industry standard IP-XACT.Single-handedly implemented Qsys streaming interface support, including modelling inJava, IP GUIs, adapter insertion logic, and adapters in Verilog & VHDL.Co-authored the Avalon Streaming specification, which has since become the standardspecification for all of Altera's communications, packet processing, DSP, and Video IP.

Provided world-wide support of Altera's POS-PHY 4 IP core, interacting with Altera's major customers, troubleshooting issues, and developing training and other collateral.Resolved a major issue for Altera's 2nd biggest customer, involving multiuple high-tech companies on a shared project. Work included crisis management, daily reports to the VP of Altera’s IP Business Unit, and daily technical conference calls with all parties in both English and Japanese. As a result, the problem was solved, and Altera ended up with good will and a strong relationship with a major customers. Won Altera's "Friends of the field" award that year for this project.

Authored various FPGA device specifications, including• The specification of the flow of data through AcceLight’s 1.28Tbps GMPLS switch.• OC-12 to OC-192 overhead processor FPGAs.• 20 Gbps format converter FPGA with test frame insertion & extraction.• ingress & egress TDM cross-connect processors & MPLS packet processorsDeveloped & delivered the Technical Training Program & Customer Trials for customers,channel partners, and AcceLight staff.Managed a team of eight engineers during a 4 week trial in Tokyo, Japan, includinginstallation, relationship management, customer instruction, and test demonstration.

Specified & implemented a twin OC-12 POS framer in a Xilinx Spartan-II device, includingSONET/SDH framing, overhead processing, and packet-over-sonet encapsulation.Specified & implemented a search engine using Content Addressable Memory devices, ableto support 2 Gigabit Ethernet ports.Project lead for the design of an OC-12 Line Interface card for a chassis-based router.Introduced Boundary Scan (JTAG) testing to the hardware and production teams, andimplemented JTAG testing on L2/L3 routers.

Designed hardware, FPGA, and embedded software for optical networking devices.

Designed hardware, FPGAs, and embedded software for Optical Networking equipment.Project manager & designer for a project to extend a single ISDN BRI on fiber-optic cable,and for an E1 version of an existing T1 ISDN Line Extender.Designed a flexible, general purpose communications driver for the MC68360 processor.Designed FPGA and driver for a standards compliant Bit Error Rate Tester system.