Kent Orthner Email & Phone Number

Santa Cruz, CA, US

Santa Clara, California, US

Santa Clara, California, US

Silicon architect for the Achronix flagship device SoC. Responsible for architecture and development of all hardened logic in our devices, including PCIe, Ethernet, CPU, and external memory, as well as all specialized FPGA tiles, such as BRAMs, DSPs, machine learning tiles, and the NoC. Architect and visionary of the Achronix 2D Noc hardware and software.

Santa Clara, California, US

Santa Clara, California, US

Campbell, CA, US

My responsibilities include managing the Software & Hardware organizations, including responsibility for high-quality and on-time implementation of all of Arteris' products. our recent focus is highly configurable cache-coherent interconnect IP.My responsibilities have included:* Growing the HW and SW teams.* Establishing test and quality reporting metrics.

Leads a large engineering staff, with 5 teams across 3 continents.Responsible for the System Design, IP Infrastructure, Debug & Instrumentation, and Quartus Programmer portions of Altera’s SW portfolio, as well as the test platform for new device checkout.Has grown a strong multi-site engineering & management team, growing and mentoring engineers and.

Architected and implemented the proof-of-concept Qsys NOC interconnect, as Master’sthesis. Subsequently led the team to develop and productize it as “Qsys” in a fraction ofthe time taken to develop SOPC Builder, the tool that Qsys replaced.Initiated and grew the Hw.tcl IP platform to where it supports all of Altera’s IP, andprovides ease-of-use and.

Provided world-wide support of Altera's POS-PHY 4 IP core, interacting with Altera's major customers, troubleshooting issues, and developing training and other collateral.Resolved a major issue for Altera's 2nd biggest customer, involving multiuple high-tech companies on a shared project. Work included crisis management, daily reports to the VP of Altera’s.

• Authored various FPGA device specifications, including
• The specification of the flow of data through AcceLight’s 1.28Tbps GMPLS switch.
• OC-12 to OC-192 overhead processor FPGAs.
• 20 Gbps format converter FPGA with test frame insertion & extraction.
• ingress & egress TDM cross-connect processors & MPLS packet processorsDeveloped & delivered the Technical Training Program & Customer Trials for customers,channel partners, and AcceLight staff.Managed a team of eight.

Curitiba, BR

Specified & implemented a twin OC-12 POS framer in a Xilinx Spartan-II device, includingSONET/SDH framing, overhead processing, and packet-over-sonet encapsulation.Specified & implemented a search engine using Content Addressable Memory devices, ableto support 2 Gigabit Ethernet ports.Project lead for the design of an OC-12 Line Interface card for a.

Designed hardware, FPGA, and embedded software for optical networking devices.

Designed hardware, FPGAs, and embedded software for Optical Networking equipment.Project manager & designer for a project to extend a single ISDN BRI on fiber-optic cable,and for an E1 version of an existing T1 ISDN Line Extender.Designed a flexible, general purpose communications driver for the MC68360 processor.Designed FPGA and driver for a standards.

Master Of Engineering (M.Eng.), Electrical Engineering

B.A.Sc, Computer Engineering