Kamal Preet Singh Bhatia Email & Phone Number

Client: Ti India (Dsps- Armbu)

Working in Static Timing Closure for SoC (45nm node)IOSTA Methodology and Timing closureCore Timing closure

Client: Ti Dallas (Dsps Group)

SoC Timing ClosureIO timing ClosureGLS Support

Gurgaon

Complete Datapath implementation and IntegrationProtocols worked on 1G Ethernet, 1G/2G Fibre Channel and 10G XAUI on backend.Complete RTL to Bit image generation ownership along with Integration of hardware with System and Application software.Issue debugging and Timing Checks for DDR Memory interface logic.Worked on CN4200 Products (Transport division) of CienaPacket based switching Cards like ESOM (Release 7.0, 7.0.1 and 7.1) and EM6http://www.ciena.com/products/ESOM_overview.htm

ASIC Design,SoC Design Implementation, Design Integration Synthesis , Equivalence and Timing closure.System C based Architecture ModelllingTLM level System Verification IP and SoC Subsystem.

IP Qualification involving Hardening of ARM 926EJS core asper SoC Architecture requirmentComplete Integration, DFT BIST logic integration and validation of the Integrated IP.SoC Verification of Telcom Chip using proprietary Perl based Verification environment.Constraint Random Verification, Coverage (RTL and FSM)

B.E, Electronics & Communication

Activities and Societies: Debate Team, ISTE Member,College Football and Cricket Team

Hsc & Ssc, Computer Science