• Having 18+ years of experience in Analog/RF/Memory/custom IC Layout and Team/Project Experience.• Choosing the foundry and process for the product development based on the different design metrics and cost.• Validating the post tape out reticle designs and signing off for mask preparation.• Analyzing different IC testing results like R3D, OBIRCH and SEM delayering and suggesting the best possible solutions.• Methodology selection for the layout flow, on time and cost metrics basis.• Directing, leading and motivating workforce; imparting continuous on job training for accomplishing greater operational effectiveness / efficiency.• Working on succession planning of the workforce, rendering technical guidance to the team, shift management activities, appraising the member’s performance & providing feedback.• Experience in hiring top talent and responsible for developing Layout teams and catering the company’s / client's requirements.• Experience in multiple Tape-out’s and Tape-in’s.• Experience working with global teams, tracking projects and ensuring teams meet schedule without compromising on quality.• Worked with the leading semiconductor companies spanning different geographies on diverse process nodes from the leading fabs.• Solid understanding of DRC's, DFM and process issues at process nodes ranging from 0.6um to 10nm.• High knowledge in advance process improvements like double patterning, context dependency layouts, etc. CMOS, Bi-CMOS & Mixed Signal Process Experience.• Experience in Process Nodes: 10nm, 14nm, 130nm (Samsung Foundry), 16nm, 65nm, 130nm, 180nm (TSMC Foundry), 20nm, 28nm (Global Foundry), 22nm FINFET (Intel Foundry), 40nm (UMC Foundry), 45nm, 90nm (NatSem Foundry), 150nm (Vanguard Foundry), 0.64um (Toko Foundry).• Hands-on experience with almost all Layout and Verification tools in industry viz., Cadence – Virtuoso, voltus-fi, Assura, Diva, Dracula; Mentor Graphics – IC Station, Calibre; Intel – Genesys; Synopsys – Hercules, IC Validator, StarRC; Tanner, etc.