Ravishankar Karthikeyan Email & Phone Number

Bengaluru, Ka, In

Santa Clara, California, Us

• Presently managing the entire Client Graphics Lineo Successful in delivering multiple SoCs to market – Intel ARC processoro Technical management, Driving Physical Design of SoC, spearheaded the team with multiplestakeholders and taking it to closureo Experience in delivering in multiple node/processes to different fabso Assembled the team from zero and involved in mentoring and scaling the engineering teamo Directly managing 80+-member team and working in a cross-site environment of 200+across India & US teams spread across 3 different design centers.

Santa Clara, California, Us

Managed a 7nm microprocessor project with a team of 40 people to be integrated into a Client SOC.Primary roles involveo Technical management and schedulingo Establish goals and metrics to be met by the team and ensure that the team executes to thesegoals• Successfully completed delivery of a 16nm & 14nm core product for Game consoleso Gained customer confidence and respect by delivering the core on schedule andmeeting/beating power performance benchmarkso Silicon results showing frequency upgraded by 10% and low powero Oversaw delivery, integration, and execution of the chip, interacted with 3 different SOCteams, providing program metrics/reports• Managed a cross-site team in the integration of the 28nm client SoC chipo Involved in determining the schedule, resource planning, tracking of IP deliverables, liaisingwith other functional teams and management.o Worked with the team in resolving Design, Timing and Electrical Analysis• Successfully delivered a 32nm Flagship server design team which was done cross-site and takenthe chip to productiono Resulted in significant revenue increase by power improvements along with frequency uplift.o Responsible for Bumps/Package, floor planning, power planning, placement, timingand electrical analysis, and physical verification checks – LVS, DRC leading to Tapeout.• Delivered successfully multiple 45nm server and desktop designso Incorporated significant Floor plan optimizations resulting in an overall SoC die areareduction of 17%.o Owned all the physical design activities from RTL to GDS• Mentored and drove assimilation programs for new college graduates of the team and ramping upthe design team• Developed business process for SoC design methodology with reuse of IPs for doing multiple SoCchips in parallel

Dallas, Tx, Us

• Delivered a USB2.0 IP design for the 65nm SoC chip used in the wireless products.• Delivered the IP with special emphasis on power and performance with added importance on thefloor plan as well.

Santa Clara, California, Us

• Responsible for design of Trace Cache Control blocks including the 4-way TLB and 8-way TAGsin a 64-bit next-generation chip.o Involved floor planning, placement, and timing analysis.• Delivered the full custom-design and integration of Clock (CK) control logic of the Opteronmicroprocessor.o Reduced the overall area of the block by greater than 10%.• Responsible for enhancements to bus unit (BU) and floating-point units (FPU) that yieldedimprovement to product performance (greater than 10% in speed).o Spearheaded cross-functional effort in the re-design of the Icache that resulted inimproving power dissipation and speed of the block by 20%.• Validated functional units of various peripherals attached to the 8051 micro-controllers in the v493-VTECH chip used in a cordless phone.

Master'S Degree, Electrical And Electronics Engineering

B.E., Electronics And Communication

Be, Ece

Education record

Education record