Verification of SAS/SATA LinkLayer using UVM.

• Verification of PCI Express based Ethernet switch congestion management block. Created Xilinx based PCI Express testbench to communicate, process, and exchange data between the data port and end point block. Simulated and verified design using Mentor Questa and Questa Verification Library.• Verification lead for Laser Control Core ASIC. Open and closed loop control techniques are used to maximize power output from the laser. Used Verilog PLI and pseudo randomization to develop chip level testbench and test patterns. Generated code coverage results using Mentor Graphics Questa.• Generated Test plan document and detailed Test Matrix spreadsheet. Conducted weekly reviews to track progress of the verification effort and test results

• Verified Multi-Clock Generator (MCG) IP block using Verilog-AMS Constrained Random Verification Methodology (CRV). Created Testbench setup, drivers, monitors, scoreboard checkers and SystemVerilog Assertions (SVA) using Freescale proprietary base class libraries (VBCL). Met code coverage requirements using Cadence nccov.• Verified Time-of-Day (TOD) IP block using Vera Constrained Random Verification Methodology. Created Testbench setup, drivers, monitors, scoreboard checkers and SystemVerilog Assertions. Met code coverage requirements using Synopsys CoverMeter.• Generated C-API test patterns for NNTV, 908LL16, 908EL32 chips to verify chip integration and test modes. Worked with Test/Product engineers to make the tests robust and tester friendly.• Defined and created NNTV SoC testbench to make the simulations work in the low power modes created using Cadence CPF tool. Generated C-API tests and assertions to verify the low power isolate, retain, and restore of data.

• Design team lead for 908QB8, 08GZ32, 908GZ60 8-bit microcontrollers in SoC and custom design methodologies. Integrated soft and hard blocks. Performed simulation and test setup. Worked with Layout designers in performing floor planning and power routing. Ran full-chip Place and Route using First Encounter and Silicon Ensemble tools. Verified chip layout using Dracula and Hercules LVS. Generated ROM masks for customer code. Archived design database using ClearCase.• Modified CAN automotive protocol module Verilog RTL to double the number of message identifiers. Synthesized Verilog RTL using Synopsys DC shell. Wrote new tests to check the modified CAN functionality. Performed place and route of CAN module using Silicon Ensemble.• Generated revisions for multiple chips to incrementally improve chip yields and fix errata. Ran stream compare between the old and the new databases to check layout differences. Performed LVS and taped out chips to internal and external fabs.• Worked with Failure Analysis Engineers to debug Customer Returns in a timely manner. Studied circuits and RTL to determine the possible failure nodes and identified them on the layout for probing.• Created test mode and padring specs. Conducted pre and post tape out reviews. Generated DFMEA and QS9000 Automotive Quality checklists. Provided input to the Project Manager in creating project schedules.

• Modified and improved a C program to generate Aliasing statistics for Multiple Input Signature Register (MISR), parallel load CRC. Sample size for the Aliasing and run time was considerably improved using Hash Table techniques.• Defined design methodologies, supported day to day design activities, installed CAD software, maintained licenses of design software, wrote shell scripts to automate the design process, helped new users in setting up their CAD environment, learned new tools and introduced them to users.

• Involved in the development of internal CAD tool TACH (Timing Analyzer using Circuit Hierarchy), used to verify static timing of CMOS VLSI designs. Used Perl language to create user interface.