Demonstrated a timing channel and covert channel attack on a real system consisting of a multicore processor and a shared hardware accelerator. Designed a communication protocol using Manchester Coding across the covert channel.Developed a design automation approach using Xilinx Vivado HLS and target FPGA Zynq-7000 that demonstrates a protection scheme to eliminate timings channels in shared hardware accelerators.

Proficiently redesigned the control schematics and network architecture, data point, valve selection procedures and schedules for HVAC, Building Management Systems and Extra Low Voltage systems.

Assisted the projects department in the Inspection Test Plan procedure for transmitters assembled at the manufacturing unit.Executed quality checks and verified certification documents of the transmitters in presence of the vendors