• Teaching Assistant for VLSI Design course.• Guided 50+ students for 8 hours/week in VLSI experiments using Cadence Virtuoso.• Assisted with schematics, delay, power/energy analysis, layout design, and Monte Carlo and Process Corner analysis.• Provided one-on-one support to students in debugging errors and warnings and cleared doubts about the course content.

• Event Leadership: Orchestrated over 26 impactful club events, including two major paid events.• Financial and Resource Management: Successfully steered the club to a debt-free status while also ensuring the upkeep and regular maintenance of musical instruments and the music room

Title - Aging Analysis of CMOS based Synaptic Circuits.Faculty Advisor - Dr. Sonal SinghalProgram - Opportunities for Undergraduate Research Program (OUR).• Implemented CMOS-based synaptic circuits using 45 nm technology on Cadence Virtuoso and carried out degradation analysis due to reliability issues using Cadence RelXpert.• Calculated synaptic weight values to achieve a peak output current of 30nA for a 10ms input spike, enabling performance comparison between various circuits.• Characterized circuit performance by calculating percentage change in key performance metrics over a 10 year life span at temperatures ranging from 25 °C to 125 °C.• Conference Paper published and Poster Presented at IEEE EDTM Conference 2024

• Communication Bridge: Served as the first primary liaison between the class group, faculty and the administration for the batch as the transition from online classes to offline classes took place.