My contributions were as below:• Logically modeled networking devices in software and wrote unit and integration tests to verify functionality.• Added software support in Java and Python to model the behavior of an AWS Transit Gateway• Characterized the packet encapsulation behaviour of Riverbed Steelhead WAN Accelerators and Interceptor by using a combination of VMs and real devices, allowing Veriflow to model the Interceptor in its code.• Created several testbeds with Cisco, Arista, Juniper and Fortinet routers, switches and firewalls, with each testbed aimed at evaluating particular features of Veriflow’s product. These testbeds were created in the GNS3 network simulator.

I was a graduate teaching assistant for the Computer Organization and Design course. My responsibilities involved helping students with their processor design assignments in SystemVerilog, setting and grading exam questions, as well as holding weekly office hours. Each semester, I would mentor several teams of students for their projects which involved creating a pipelined processor for the LC3b ISA, as well as a L1 and L2 cache hierarchy.

Graduate Teaching Assistant for ECE 110 at UIUC. Conducted lab sessions for freshmen students which covered basic circuits involving resistors, capacitors, diodes, etc