DRAM CIRCUIT DESIGN AND VERIFICATIONCXL DRAM PRODUCT IO CIRCUITS AND IP DELIVERY LEADTOP SHCEMATIC BUILTUP AND CAD INTERACTIONS LEAD

DESIGN OF COMPLETE X40 DDR MULTI PHY. TECHNICAL DELIVERY HEAD FOR INTEL FOLSOM Account

DDR PHY OWNERSHIP, DDR4 RX redesign in 28nM. PHY customization for INTELHATHY PHY customization for Qualcom

DDR & GPIO solutions for FPGA2 PATENTS GRANTED

Individual contributor responsible for next generation FPGA IO design.Define specifications, architecture and product road maps, based on interaction with marketing team.Ex• ~6 years at XILINX Ireland & Xilinx Hyderabad as Staff IC circuit design Engineer• 3.3v KINTEX IOs (HRIO) MRD to GDS delivery & project management• MIPI D-phi feasibility and project management• DDR3 IO, PVT compensated IO design• Bench verification  Spartan, kintex, and Artix product lines.• Innovation awards for Power sequence elimination in FPGAs• 2 patents granted,3 patents applied

Design and develop 90nm SSTL15 IO solution for LSI MCMs.DDR2 High speed transmitter and receiver design Design of RC coupled ESDbefore the LSI operations CLOSE IN DUBAI

Worked as circuit designer for Analog Phase interpolator for PCI Express interface.Clock data recovery circuits of PCI express gen1 circuits at 2.5Gbps. Participated in charge pump based active decoupling capacitor (ADC).Reduced the on die DECAP area by 35% of the previous generation DECAP area. This ADC is extensively used in Intel FSB based GMCH and other I/F.Gained expertise in PI based CDR for high speed serial links (PCI EXPRESS).Worked as a validation lead for PCI express interface at Intel. Both pre silicon and post silicon.Ran Task force meetings and brain storming sessions to debug the PCI express link errors seen in the post silicon validation, successfully root caused the issue, got good exposure to debug by Pico probing. Ran a Task force meetings gathering the experts when ESD failure was observed on the silicon for CDM, due to failure of 1 ohm rule.As a part of post silicon validation, I setup the BERT tester and successfully gathered the jitter tolerance data for gen1 PCI express.Post silicon debug is the core expertise I gain by automating the test setupDesigned active decoupling capacitor for Front side bus (FSB) that reduced the on die decap by 20%.This ACTIVE DECAP is tested in silicon and is in use in all Intel MCH CHIP.Lab automation software: automated data collection for PCI expresses silicon validation that will be for generations.

Started as ESD & I/O ; ESD Circuit design Engineer.Designed multi-voltage tolerant I/O circuits.Did Cell library Characterization.Drain Extended CMOS (DEMOS) Circuit design for high voltage tolerant IOs.Developed Scripts to check the gate oxide integrity in the I/O Circuits.

worked on head up Displays and Weapon aiming computers Automated test bench construction Engineer for Indian Air force consutancy project executed at IIT kanpur.