Have 6+years of working experience on Physical design and Physical verification. Worked multiple projects on 7 & 6nm, handled critical Heirachal blocks.PD Key skills:> Block level Design planning, placement, clock tree synthesis and routing.> Implementation of Functional & Timing ECO's and aware of Scan stitching flow for flops added in eco phase.> Signoff check : PV, EMIR, STA, LEC and CLP clean-up.PV skills:> Calibre drc fixing , LVS , ESD 1 ohm & perc , ERC, DFM score , Gaurdring and Antenna.> Handled full chip level PV clean-up and integration support.EDA tools:IC Compiler 2 , Calibre DRV , Prime time and Redhawk