ASIC RTL Design engineer with 3 years experience. Skills include System verilog, Compilation debugs, PLDRC checks, Clock Domain Crossing analysis, Clock Controller generation, Integration of various sub-ip's and conjunctively discussing test plans with verification teams and timing issues with Netlist team on the latest design changes.Seeking a challenging and rewarding opportunity in Design with an organization which recognizes and utilizes my true potential while nurturing my technical skills.